Trading Speed for Low Power by Choice of Supply and Threshold Voltages

IEEE Journal of Solid-State Circuits

Volumn 28, Issue 1, 1993, Pages 10-17

  Liu, Dake ^a   Svensson, Christer ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT THEORY; ELECTRIC POWER UTILIZATION; GATES (TRANSISTOR); PARAMETER ESTIMATION; PERFORMANCE; VLSI CIRCUITS; VOLTAGE CONTROL;

HIGH PERFORMANCE COMPLEX CHIPS; SUPPLY VOLTAGES; THRESHOLD VOLTAGES;

CMOS INTEGRATED CIRCUITS;

EID: 0027256982     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.179198     Document Type: Article

References (20)

1. M. Kakumu and M. Kinugawa, “Power supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI,” IEEE Trans. Electron Devices, vol. 37, no. 8, pp. 1902–1908, Aug. 1990.
2. J. L. Hennessy and N. P. Jouppi, “Computer technology and architecture: An evolving interaction,” IEEE Trans. Compute vol. 24, no. 9, pp. 18–29, 1991
3. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, (VLSI Systems Series). Reading, MA: Addison Wesley, 1990.
4. M. Afghahi and C. Svensson, “Performance of synchronous and asynchronous schemes for VLSI systems,” IEEE Trans. Comput, vol. 41, no. 7, pp. 858–872, July 1992.
5. N. G. Einspruch, VLSI Electronics Microstructure Science, vol. 18, Advanced MOS Device Physics. New York: Academic, 1989, pp. 237–273.
6. H. Masuda, J.-I, Mano, R. Ikematsu, H. Sugihara and Y. Aoki, “A submicrometer MOS transistor I~V model for circuit simulation,” IEEE Trans. Computer-Aided Design, vol. 10, no. 2, pp. 161–169, Feb. 1991.
7. A. L. Silburt, R. C. Foss and W. F. Petrie, “An efficient MOS transistor model for computer-aided design,” IEEE Trans. Computer-Aided Design, vol. CAD-3, no. 1, pp. 104–111, Jan. 1984.
8. P. C. Chan, P. Liu, S. K. Lau, and M. Pinto-guedes, “A subthreshold conduction model for circuit simulation of submicron MOSFET,” IEEE Trans. Computer-Aided Design, vol. CAD-6, no. 4, pp. 574—581, July 1987.
9. Z. Yang, Introduction for Design Methodology of ULSI. Bejing: Tsinghua University Publishing, 1990, pp. 98–99 (in Chinese).
10. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. New York: Holt, Rinehart and Winston, 1987, 55.
11. S. Shao-Shiun Chung, “A charge-based capacitance model of short-channel MOSFET’s,” IEEE Trans. Computer-Aided Design, vol. 8, no. I. 1–7, Jan. 1989.
12. G. W. Taylor, W. Fichtner, and J. G. Simmons, “A description of MOS internal capacitances for transient simulations,” IEEE Trans. Computer-Aided Design, vol. CAD-1, no. 4, pp. 150–156, Oct. 1982.
13. D. Deschacht, M. Robert, and D. Auvergen, “Explicit formulation of delay in CMOS data paths,” IEEE J. Solid-State Circuits, vol. 23, no. 5, pp. 1257–1264, Oct. 1988.
14. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design. Reading, MA: Addison-Wesley, 1985, 144–148.
15. E. H. Li and H, C. Ng, “Parameter sensitivity of narrow-channel MOSFET’s,” IEEE Electron Device Lett., vol. 12, no. 11, pp. 608–610, Nov. 1991.
16. M. Conti, C. Turchetti, and G. Masetti, “A new analytical and statistical-oriented approach for the two dimensional threshold analysis of short-channel MOSFETs,” Solid-State Electron., vol. 32, no. 9, pp. 739–747, 1989.
17. J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits. vol. 24, no. 1, pp. 62–70, Feb. 1989.
18. M. Zambuto, Semiconductor Devices. New York: McGraw-Hill, 1989.
19. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power CMOS digital design,” IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473—484, Apr. 1992.
20. E. Vittoz and J. Fellrath, “CMOS analog integrated circuits based on weak inversion operation,” IEEE J. Solid-State Circuits, vol. SC-12, no. 3, June 1977.