Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip

IEEE Transactions on Computers

Volumn 39, Issue 8, 1990, Pages 983-992

  Chan, Pak K ^a   Schlag, Martine D F ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Adders; carry skip adders; carry skip block sizing; CMOS circuit design; Manchester adders

Indexed keywords

COMPUTER PROGRAMMING--ALGORITHMS; INTEGRATED CIRCUITS, CMOS; INTEGRATED CIRCUITS, VLSI;

CARRY-SKIP ADDERS; MANCHESTER ADDERS; RC TIMING MODEL;

COMPUTERS, DIGITAL;

EID: 0025470946     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.57038     Document Type: Article

References (15)

1. P. K. Chan and K. Karplus, “Computing signal delay in general RC networks by tree/link partitioning,” IEEE Trans. Comput.-Aided Design Integrated Circuits Syst., July 1990. Also in Proc. 26th ACM/IEEE Design Automat. Conf., Las Vegas, NV, June 1989.
2. E. R. Barnes and V. G. Oklobdzija, “New scheme for VLSI implementation of fast ALU,” IBM Tech. Disci. Bull, vol. 28, no. 3, pp. 1277–1282, Aug. 1985.
3. G. A. Blaauw, Digital System Implementation. Englewood Cliffs, NJ: Prentice-Hall, 1976, pp. 47–50.
4. A. Guyot, B. Hochet, and J.-M. Muller, “A way to build efficient carry-skip adders,” IEEE Trans. Comput., vol. C-36, no. 4, pp. 1144–1151, Oct. 1987.
5. D. Heron, M. Kruckenberg, SolidState, and F. Wei, “A modified Manchester carry-skip adder,” UCSC-CRL-89-10 Tech. Rep. Comput. Eng., Univ. of California, Santa Cruz, Nov. 1989.
6. T. Kilburn, D. B. G. Edwards, and D. Aspinall, “A parallel arithmetic unit using a saturated transistor fast-carry circuit,” Proc. IEE, pt. B, vol. 107, pp. 573–584, Nov. 1960.
7. M. Lehman and N. Burla, “Skip techniques for high-speed carry-propagation in binary arithmetic units,” IRE Trans. Electron. Comput., vol. EC-10, no. 4, pp. 691–698, Dec. 1961.
8. S. Majerski, “On determination of optimal distributions of carry skips in adders,” IEEE Trans. Electron. Comput., vol. EC-16, no. 1, pp. 45-58, Feb. 1967.
9. C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, pp. 150–152.
10. V. G. Oklobdzija and E. R. Barnes, “Some optimal schemes for ALU implementation in VLSI technology,” in Proc. 1th Symp. Comput. Arithmetic, June 1985, pp. 2–8.
11. M. Pomper, W. Beifuss, K. Horninger, and W. Kaschte, “A 32-bit execution unit in an advanced NMOS technology,” IEEE J. SolidState Circuits, vol. SC-17, no. 3, pp. 533–538, June 1982.
12. P. Penfield, Jr. and J. Rubinstein, “Signal delay in RC tree networks,” in Proc. 18th ACM/IEEE Design Automat. Conf., June 1981, pp. 613–617.
13. E. Soutschek, M. Pomper, and K. Horninger, “PLA versus bit slice: Comparison for a 32-bit ALU,” IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp. 584–586, June 1982.
14. S. Turrini, “Optimal group distribution in carry-skip adders,” Digital Western Res. Lab. Res. Rep. No. 2, Feb. 1989.
15. N. Weste and K. Eshraghian, Principles of CMOS Design: A Systems Perspective. Reading, MA: Addison-Wesley, 1985, pp. 322–325.