Power-Delay Characteristics of CMOS Adders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 2, Issue 3, 1994, Pages 377-381

  Nagendra, Chetana ^a   Owens, Robert Michael ^a   Irwin, Mary Jane ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

Power delay product; sizing; static CMOS adders; transistor

Indexed keywords

CMOS ADDERS; POWER DELAY CHARACTERISTICS; TRANSISTOR SIZING;

ALGORITHMS; CARRY LOGIC; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; DELAY CIRCUITS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; NUMBER THEORY; TIMING CIRCUITS; TRANSISTORS; COMPUTER SIMULATION; COMPUTER SOFTWARE; ELECTRIC LOSSES; LOGIC DESIGN;

ADDERS;

POWER DELAY CHARACTERISTICS; SOFTWARE PACKAGE PERFLEX;

EID: 0028501885     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.311649     Document Type: Article

References (19)

1. D. E. Atkins, “Introduction to the role of redundancy in computer arithmetic,” Computer, pp. 74–77, Jun. 1975.
2. A. Avizienis, “Signed-digit number representation for fast parallel arithmetic,” IRE Trans. Electronic Comput., p. 389, 1961.
3. R. G. Brayton and R. Rudell et al, “MIS: A multiple-level logic optimization system,” IEEE Trans. Computer Aided Design, vol. 6, no. 6, pp. 1062–1081, Nov. 1987.
4. R. P. Brent and H. T. Kung, “A regular layout for parallel adders,” IEEE Trans. Comp., vol. C-31, no. 3, 260–264, Mar. 1982.
5. R. Burch, F. N. Najm, D. Yang, and T. N. Trick, “A Monte Carlo approach for power estimation,” IEEE Trans. VLSI Syst., vol. 1, no. 1, pp. 63–71, 1993.
6. T. K. Callaway and E. E. Swartzlander Jr., “Estimating the power consumption of CMOS adders,” in Proc. 11th Symp. on Comp. Arithmetic, June 1993, pp. 210–219.
7. A. Chandrakasan, M. Potkonjak, J. Rabaey, and R. Brodersen, “An approach for power minimization using transformations,” in IEEE VLSI Signal Process. Workshop, pp. 41–50, June 1992.
8. A. Chandrakasan, S. Sheng, and R. Brodersen, “Low power CMOS digital design,” IEEE J. Solid-state Circ., pp. 685–691, Apr. 1992.
9. K. M. Chu and D. L. Pulffey, “A comparison of CMOS’ circuit techniques: Differential cascade switch logic versus conventional logic,” IEEE J. Solid-state Circ., vol. 22, pp. 528–532, Aug. 1987.
10. M. Cirit, “Estimating dynamic power consumption of CMOS circuits,” in ICCAD, pp. 534–537, 1987.
11. S. Devadas, K. Keutzer, and J. White, “Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation,” IEEE Trans. Computer Aided Design, vol. 11, no. 3, pp. 373–383, Mar. 1992.
12. J. P. Fushbum and A. E. Dunlop, “TILOS: A posynomial programming approach to transistor sizing,” in Proc. ICCAD, pp. 326–328, 1985.
13. S. M. Kang, “Accurate simulation of power dissipation in VLSI cir-cuits,” IEEE J. Solid-State Circ., vol. SC-21, no. 5, pp. 889–891, Oct. 1986.
14. T. P. Kelliher, R. M. Owens, M. J, Irwin, and T.-T. Hwang, “ELM—A fast addition algorithm discovered by a program,” IEEE Trans. Comput., vol. 41, no. 9, Sept. 1992.
15. S. Kim, “CMOS VLSI layout synthesis for circuit performance,” Ph.D. dissertation, The Penn State Univ., Univ. Park, 1992.
16. S. Kim, R. M. Owens, and M. J. Irwin, “Experiments with a performance driven module generator,” in Proc. DAC, June 1992, 687–690.
17. Meta-Software, HSPICE User’s Manual version H92. Campbell, CA: Meta-Software, 1992, 1300 White Oaks Road, Campbell, CA 95008.
18. C. Sechen and A. L. Sangiovanni-Vincentelli, “The Timberwolf routing package,” in Proc. Custom Integral Circuit Conf., May 1984.
19. G. W. Summers, W. S. Peters, and C. P. Armstrong, Basic Statistics in Business and Economics. Belmont CA: Wadsworth, 1981, ch. 8.