Silicon MOS Transconductance Scaling into the Overshoot Regime

IEEE Electron Device Letters

Volumn 14, Issue 8, 1993, Pages 375-378

  Pinto, Mark R ^a   Sangiorgi, Enrico ^b   Bude, Jeff ^a  

^a LUCENT TECHNOLOGIES   (United States)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; OPTIMIZATION; SEMICONDUCTING SILICON;

CHANNEL LENGTH; LOW-FIELD INVERSION LAYER CONTROL; LOW-FIELD MOBILITY; OVERSHOOT REGIME; SILICON MOS TRANSCONDUCTANCE SCALING; VELOCITY OVERSHOOT;

MOS DEVICES;

EID: 0027640789     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.225584     Document Type: Article

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