Evolution of the MOS Transistor-From Conception to Vlsi

Proceedings of the IEEE

Volumn 76, Issue 10, 1988, Pages 1280-1326

  Sah, Chih Tang ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, VLSI; LITHOGRAPHY; PATENTS AND INVENTIONS; TRANSISTORS, BIPOLAR; TRANSISTORS, FIELD EFFECT;

DYNAMIC RAM CELLS; INTERCONNECT WIRING DELAY; SILICON MOSFET; SUBMICRON LITHOGRAPHIC TECHNOLOGIES; TRANSISTOR SWITCHING SPEED;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0024087662     PISSN: 00189219     EISSN: 15582256     Source Type: Journal    
DOI: 10.1109/5.16328     Document Type: Article

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64. These were recorded in product data sheets, titled “Fairchild Silicon Transistors,” during 1959 to 1961. The transistor number, data sheet number, date of issue and transistor type are: 2N696: SL-4/1(npn, mesa), SL-5/4(9-61, npn, planar); 2N706: SL-13/3(6-61, npn, mesa, gold-doped, switch); 2N709: SL-52/3(2-62, npn, planar, gold-doped, switch); 2N869: SL-42/3(6-61, pnp, planar); 2N914: SL-36/3(6-61, npn, planar, epitaxial, gold-doped, switch); 2N1131: SL-6/4(6-61, pnp, mesa); 2N1613: SL-17/4(9–61, npn, planar).
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94. For a recent report on Wanlass, see C. Barney, “He started MOS from scratch,” Electronics Week, p. 64, Oct. 8, 1984.
95. The acroynm MOST given in the title of the Fairchild technical memorandum [91] did not appear in the article published in the 1963-ISSCC proceeding [90]. After twenty-six years, my recollection on the reason for this omission is hazy and I seem to recall my anxiety after F. Wanlass told me during Christmas 1962 about G.E. Moore's remark discussed in the text which probably resulted in its omission. However, it was used in the first article I wrote on the characteristics of the MOS transistor [96].
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105. E. Kooi, “Effects of low temperature heat treatments on the surface properties of oxidized silicon,” Philips Res. Rep., vol. 20, pp. 578-594, Oct. 1965 who stated, “. Balk has proposed that the effect of hydrogen during annealing (heat treatment of oxidized silicon in 300–500?C range) is due to a chemical saturation with H atoms of certain unsaturated bonds (dangling bonds) at the oxide-silicon interface. The experiments to be described in this paper suggest that the main effect of water and an aluminum electrode on the oxide during low-temperature heat treatments has to be explained in a similar way, although charge redistribution (due to sodium ion contamination of the early oxidation technology) in the oxide-silicon system cannot always be neglected.”
106. P. Balk, P.G. Burkhardt, and L.V. Gregor, “Orientation dependence of built-in surface charge on thermally oxidized silicon,” Proc. IEEE, vol. 53, no. 12, pp. 2133–2134, Dec. 1965.
107. J.F. Delord, D.G. Hoffman, and G. Stringer, “Use of MOS capacitors in determining the properties of surface states at the Si-Si02 interface,” Bull. Amer. Phys. Soc, serial II, vol. 10, no. 4, abstract KF9, 546, Apr. 26, 1965.
108. Y. Miura, “Effect of orientation on surface charge density at silicon-silicon dioxide interface,” Japan. J. Appl. Phys., vol. 4, no. 12, pp. 958–961, Dec. 1965.
109. P. Handler, “Electrical properties of a clean germanium surface,” in Semiconductor Surface Physics, R.H. Kingston, Ed. Philadelphia, PA: University of Pennsylvania Press, 1957, pp. 23–51. See also a detailed recent review and a new and corrected tabulation of the orientational dependences of the dangling bond density by Sah [29], [110].
110. C.T. Sah, “Interface traps on oxidized Si from X-ray photoemission spectroscopy, MOS diode admittance, MOS transistor and photogeneration measurements,” in Properties of SILICON, London, England: INSPEC, The Institution of Electrial Engineers, section 17.3, pp. 512-520, May 1988. Available from INSPEC Dept., IEEE Service Center, 455 Hoes Lane, P.O. Box 1331, Piscataway, N] 08855–1331. See also section 17.1 cited in [29].
111. R.E. Kerwin, D.L. Klein, and J.C. Sarace (Bell Telephone Laboratories), “Method for making MIS structures,” U.S. Patent 3 475 234, filed Mar. 27, 1967, issued Oct. 28, 1969.
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114. R.W. Bower and H.G. Dill, 1966 IEDM paper 16.6 which covered the first ion implanted MOSFET using self-aligned aluminum metal gate.
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121. D. Kahng, “Field effect semiconductor apparatus with memory involving entrapment of charge carriers,” U.S. Patent 3 500 142, filed June 5, 1967, issued Mar. 10, 1970.
122. D. Frohman-Bentchkowsky, “Floating gate transistor and method for charging and discharging same,” U.S. Patent 3 660 819, filed June 15, 1970, issued May 2, 1972.
123. See also D. Frohman-Bentchkowsky, “A fully decoded 2048-bit electrically-programmable MOS-ROM,” in ISSCCDigest of Tech. Papers, pp. 80-81, Feb. 1971, and a full size paper with the same title in IEEE J. Solid-State Circuits, vol. SC-6, no. 10, pp. 301–306, Oct. 1971.
124. D. Frohman-Bentchkowsky, “Memory behavior in a floating-gate avalanche-injection MOS (FAMOS) structure,” Appl. Phys. Lett., vol. 18, pp. 332–334, Apr. 15, 1971.
125. D. Frohman-Bentchkowsky, “FAMOS-A new semiconductor charge storage device,” Solid-State Electron., vol. 17, pp. 517–529, 1974.
126. J.F. Verwey, “Nonvolatile semiconductor memories,” Advances in Electronics and Electron Physics, vol. 41, pp. 249–309, 1976.
127. J.J. Chang, “Nonvolatile semiconductor memory devices,” Proc. IEEE, vol. 64, no. 7, pp. 1039–1059, July 1976.
128. Y. Nishi and H. lizuka, “Nonvolatile memories,” in Silicon Integrated Circuits, Dawon Kahng, Ed. New York, NY: Academic Press, 1981, pp. 121–251.
129. W.I. Kinney, W. Shepherd, W. Miller, J. Evans, and R. Womack (Krysalis Microelectronic), “A nonvolatile memory cell based on ferroelectric storage capacitors,” in Technical Digest of the 1987 IEDM, paper 3.9, pp. 850–851, Dec. 1987.
130. See also “Ferroelectrics: the latest in RAD-hard, nonvolatile memory,” Electronics, p. 162, Jan. 7, 1988.
131. For a detailed discussion of some speculated advantages of the nonvolatile and highspeed ferroelectric MOS memory, see Section IV, titled FEFET, on page 1053 in J.J. Chang's review cited in 127. which also listed twenty-eight references of research reports on using ferroelectric for memory during 1967 to 1974.
132. R. Womack, W. Kinney, B. Shepherd, B. Miller, and J. Evans, “An experimental 512-bit nonvolatile memory with ferroelectric storage cell,” submitted to the IEEE Int. Solid State Circuit Conf., San Francisco, CA, Feb. 12, 1988. Manuscript available from Bill Miller. See also “Krysalis Co-Founders leave in realignment,” Electronic News, p. 24, July 4, 1988; “Krysalis to file Chapter 11,” Electronic News, p. 22, Sept. 19, 1988.
133. S. Sheffield-Eaton, D.B. Bulter, M, Parris, D. Wilson, and H. McNeillie, “A ferroelectric nonvolatile memory,”; in IEEE Int. Solid State Circuits Conf. (ISSCC), Digest of Technical Papers, XXXI, pp. 130-131, Feb. 1988. IEEE Cat. No. 88CH2562–7. Publisher: Lewis Winner, Coral Gables, FL 33134.
134. For an early review of the MOS memory cell designs, see L.M. Terman, “MOSFET memory circuits,” Proc. IEEE, vol. 59, no. 7, pp. 1044–1058, July 1971.
135. J.D. Schmidt, “Integrated MOS transistor random access memory,” SolidStateDesign, pp. 21–25, Jan. 1965. A256word (72 bit/word) silicon BJT memory system using the six-transistor cell and 36-bit per chip (60 x 80 square mil area) was described by H.A. Perkins and J.D. Schmidt [136].
136. H.A. Perkins and J.D. Schmidt, “An integrated semiconductor memory system,” in Proceedings of IEEE Fall Joint Computer Conf, pp. 1053–1064, 1965, which used the CTμL (Complementary Transistor Micrologic) elements.
137. For a comprehensive compilation of silicon memory developments and products prior to 1972, see the collected reprint volume by D.A. Hodges, Semiconductor Memories. New York, NY: IEEE Press, 1972. See also reviews given in [138]-[142].
138. Special Issue on Semiconductor Memory, IEEE Trans. Electron Devices, vol. ED-26, no. 6, pp. 825–918, June 1979.
139. Special Issue on Logic and Memory, IEEE J. Solid-State Circuits, vol. SC-17, no. 5, pp. 790–963, Oct. 1982.
140. For a more recent survey of the silicon memory technology, see E.W. Pugh, D.L. Critchlow, R.A. Henie, and L.A. Russell, “Solid state memory development at IBM,” IBM J. Res. Develop., vol. 25, no. 5, pp. 585–602, Sept. 1981 and [141].
141. W.E. Harding, “Semiconductor manufacturing in IBM, 1957 to the present: A perspective,” IBM J. Res. Develop., vol. 25, no. 5, pp. 647–658, Sept. 1981.
142. S. Asai (Hitachi Central Research Laboratory), “Semiconductor memory trends,” Proc. IEEE, vol. 74, no. 12, pp. 1623–1635, Dec. 1986.
143. R.H. Dennard et al., “Design of ion implanted MOSFET's with very small physical dimensions,” J. Solid-State Circuits, vol. SC-9, pp. 256–268, May 1973.
144. C.N. Berglund, “The evolution of MOS process technology,” presented at a graduate seminar of the Coordinated Science Laboratory of the University of Illinois on Apr. 19, 1982, under the Intel College Seminar Program. Dr. Berglund started a laser-based semiconductor manufacturing system company (Ateq Corp. in Beaverton, OR) in 1984 see “Intel Mgr. leaves to start semicon gear Mfg. venture,” Electronic News, p. 1, 22, Jan. 9, 1984, and M. Mehler, “TAGs (Technical Advisory Groups): A form of organized bean spilling,” Electronic Business, pp. 42–44, Aug. 1, 1986. He recently left and became an independent expert consultant.
145. G.E. Moore presented a market-driven scenario on the silicon MOS integrated circuit advances to the American Electronics Association San Francisco Council, Feb. 1984. I am indebted to him for a private communication to provide the information. For other recent surveys on the price trend of the DRAM chip, see [146]-[149].
146. M.P. Lepselter and S.M. Sze, “DRAM pricing trends-the pi rule,” IEEE Circuits and Devices Mag., vol. 1, pp. 53–54, Jan. 1985.
147. R. Bambrick, “Premature erosion of DRAM priceschanging economics of memory market,” Electronic News, vol. 31, no. 1543, p. 1, Apr. 1, 1985.
148. “DRAMs near millicent per bit, speed up megabit race,” Electronic News, vol. 31, no. 1556, p. 1, July 1, 1985.
149. M.R. Leibowitz, “4Mb DRAMs: Tougher to make; tougher to sell?” Electronic Business, vol. 14, no. 1, pp. 110–114, Jan. 1, 1988.
150. J.R. Lineback, “Tl turns to EPROMs as technology driver,” Electronics Magazine, pp. 16-17, Sept. 30, 1985, and “DRAM loses ground as process driver,” Electronics Magazine, pp. 24–25, Dec. 2, 1985.
151. J. Thompson, “SRAMs lead DRAM in BICMOS process push,” Electronic News, p. 23, July 4, 1988.
152. V.L. Rideout, “One-device cells for dynamic random-access memories: A tutorial,” IEEE Trans. Electron Devices, vol. ED-26, no. 6, pp. 839–852, June 1979.
153. P.K. Chatterjee, G.W. Taylor, R.L. Easley, H.-S. Fu, and A.F. Tasch, Jr., “A survey of high-density dynamic RAM cell concepts,” IEEE Trans. Electron Devices, vol. ED-26, no. 6, pp. 827–839, June 1979.
154. The data plotted in the figures and discussed in the text were gathered by the author from the following sources up to the latest issues. Digests of Technical Papers of the following annual conferences: ISSCC, IEDM, Symposium on VLSI Technology (U.S.-Japan), all sponsored by the IEEE. IEEE Trans. Electron Devices (monthly). IEEE J. Solid-State Circuits (bimonthly). IEEE Spectrum (monthly). Solid State Technol. (monthly). Electronic News (weekly newspaper). Electronics (biweekly). Electronic Business (biweekly). Electronic Design (biweekly). Computer World (weekly). Computer Design (monthly). Physics Today (monthly). Wall Street Journal (daily). Fortune (monthly). Sci. Am. (monthly). The author has added some new data points to the figures since the completion of the first draft on July 4, 1986, up to the date of page setting by the publisher around July 4, 1988.
155. “A Matter of Substance:.IBM has moved volume production of 1M DRAMs to 8-inch silicon wafers (photograph. and IBM claims its new 8-inch wafers can yield 450 1M DRAMS compared with 150 on a 5-inch wafers. The (increase) reportedly multiplied IBM's DRAM production in Burlington, VT., so much the company could set aside plans to put new memory capacity in its Manassas, VA, facilities.” Electronic News, photograph on p. 17, June 6, 1988.
156. S.P. Murarka, “Refractory silicides for integrated circuits,”]. Vac. Sci. Technol., vol. 17, no. 4, pp. 775–792, July/Aug. 1980.
157. A.K. Sinha, “Refractory metal silicides for VLSI applications,”/. Vac. Sci. Technol., vol. 19, no. 3, pp. 778–785, Sept./ Oct. 1981.
158. S.P. Murarka, Silicides for VLSI Applications. New York, NY: Academic Press, 1983.
159. P.A. Cargini, “Interconnect and contact technologies for VLSI applications,” in Solid State Devices 1983, Conf. Series 69, E.H. Rhoderick, Ed. London, England: The Institute of Physics, 1983, pp. 141–159.
160. F.M.d'Heurleand P. Gas, “Kinetics of formation of silicides: A review,” J. Material Res., vol. 1, no. 1, pp. 205–221, Jan./Feb. 1986.
161. R.S. Blewer, “Progress in LPCVD tungsten for advance microelectronics applications,” Solid State Technol., pp. 117–126, Nov. 1986.
162. A whole session of five papers are devoted to the tungsten interconnect technology in the 1987-IEDM last December. See papers 9.1 to 9.5, pp. 200-220, in Technical Digest, 1987 International Electron Device Meeting, IEEE Catalog No. 87CH2515–5, IEEE Inc., 445 Hoes Lane, Piscataway, NJ.
163. C. Bulinsky, “Technology in the year 2000,” Fortune, pp. 92–98, July 18, 1988.
164. H. Sunami et al., “A corrugated capacitor cell (CCC) for megabit dynamic MOS memories,” in Technical Digest, IEEE Int. Electron Device Meeting, pp. 806-808, Dec. 1982. Also published as “A corrugated capacitor cell (CCC),” IEEE Electron Device Lett., vol. EDL-4, pp. 90-91, 1983, and IEEE Trans. Electron Devices, vol. ED-31, pp. 746–753, 1984.
165. K. Nakamura, M. Yanagisawa, Y. Nio, K. Okamura, and M. Kikuchi, “Buried isolation capacitor (BIC) cell for megabit MOS dynamic RAM,” in Technical Digest of the IEEE Int. Electron Devices Meeting, pp. 236-239, Dec. 9-12, 1984. IEEE Catalog No. 84CH2099–0.
166. S. Nakajima, K. Miura, K. Minegishi, and T. Morie, “An isolation merged vertical capacitor cell for large capacity DRAM,” in Technical Digest of the IEEE Int. Electron Devices Meeting, pp. 240-243, Dec. 9-12, 1984. IEEE Catalog No. 84CH2099–0.
167. M. Wade, K. Hieda, and S. Watanabe, “A folded capacitor cell (F.C.C.) for future megabit DRAMS,” in Technical Digest of the Int. Electron Devices Meeting, pp. 244-247, Dec. 9-12, 1984. IEEE Catalog No. 84CH2099–0.
168. M. Elahy et al., “Trench capacitor leakage in Mbit DRAM,” in Technical Digest of the Int. Electron Devices Meeting, pp. 248-251, Dec. 9–12, 1984.
169. N. Lu et al., “The SPTcell-a new substrate-plate trench cell for DRAMs,” in Technical Digest of Int. Electron Device Meeting, pp. 771-772, Dec. 1-4, 1985. IEEE Publication Catalog No. 85CH2252–5.
170. H. Sunami, “Cell structures for future DRAMs,” in Technical Digest of the 1985 Int. Electron Device Meeting, pp. 694-697, Dec. 1-4, 1985. IEEE Publication Catalog No. 85CH2252–5.
171. N. Chau-chun Lu, “Advanced cell structures for dynamic RAMs,” in Proc. 1987 Symp. on VLSI-TSA, pp. 163-168, May 13–15, 1987.
172. P.K. Chatterjee was a former graduate student in the semiconductor physics course, EE/Physics 435, I taught during spring semester of 1974 at the University of Illinois in Urbana with the assistance of M. McNutt, S. Pantelides, and T.H. Ning as teaching assistants during the early 1970 offerings. Pallab was one of the best students I have taught in this advanced semiconductor physics course over the years. Chatterjee won the J.J. Ebers Award of the IEEE Electron Device Society in 1986 for leading this and other Tl's DRAM development effort.
173. W.F. Richardson and P.K. Chatterjee et al., “A trench transistor crosspoint DRAM cell,” in Technical Digest, Int. Electron Device Meeting, pp. 714-717, Dec. 1-4, 1985. IEEE Catalog No. 85CH2252–5.
174. S.K. Banerjee and P.K. Chatterjee et al., “Characterization of trench transistors for 3-D memories,” in Digest of Technical Papers, 1986 Symp. on VLSI Technology, pp. 79-80. IEEE Catalog No. 86CH2318–4.
175. For a pedestrian account, R. Ristelhueber, “Tl Redesigning 4M DRAM to fit 300-mil package by ′89,” Electronic News, vol. 32, no. 1612, p. 32, July 28, 1986.
176. R. Bambrick, “Shift to CMOS FMVs (Foreign Market Value) may hike DRAM tags,” Electronic News, p. 1, 22–23, July 4, 1988.
177. M. Inoue et al. (Matsushita Semiconductor Research Center), “A 16Mb DRAM with an open bit-line architecture,” in Technical Digest of Papers, ISSCC XXXI, pp. 246–247, Feb. 1988.
178. S. Watanabe et al. (Toshiba VLSI Research Center), “An experimental 16Mb CMOS DRAM chip with a 100MHz serial read/write mode,” in Technical Digest of Papers, ISSCC XXXI, pp. 248–249, Feb. 1988.
179. M. Aoki et al. (Hitachi Central Research Laboratory), “An experimental 16Mb DRAM with transposed data-line structure,” in Technical Digest of Papers, ISSCC XXXI, pp. 250-251, Feb. 1988. For a pedestrain account of these three papers [177]-[179], see B.C. Cole, “The next wave: 16-MBIT DRAMS FROM JAPAN,” Electronics, vol. 61, no. 4, pp. 68–69, Feb. 18, 1988.
180. A.S. Oberai, “Lithography-challenges of the future,” Solid State Technol., vol. 30, no. 9, pp. 123-128, Sept. 1, 1987. For an earlier review, see R.K. Watts and J.H. Bruning, “A review of fine-line lithographic techniques: present and future,” Solid State Technol., vol. 24, no. 5, pp. 99–105, May 1981.
181. L. Waller, “Fine tuning optical steppers,” Electronics, pp. 134–135, Oct. 15, 1987.
182. R.D. Moore, “EL systems: high throughput electron beam lithography tools,” Solid State Technol., vol. 26, no. 9, pp. 127–132, Sept. 1, 1983.
183. H.C. Pfefer, “Recent advances in electron-beam lithography for the high volume production of VLSI devices,” IEEE Trans. Electron Devices, vol. ED-26, no. 4, pp. 663–674, Apr. 1979.
184. W.D. Grobman et al., “1 μm VLSI technology: Part IV-electron-beam lithography,” IEEE Trans. Electron Devices, vol. ED-26, no. 4, pp. 360–368, Apr. 1979.
185. H.N. Yu, et al., “Fabrication of a miniature 8k-bit memory chip using electron-beam exposure,” J. Vac. Sci. Technol., vol. 112, no. 6, pp. 1297–1300, Nov./Dec. 1975.
186. K.J. O'Connor and R.A. Kushner (Bell Labs.), “A 5ns 4K x 1 NMOS static RAM,” in Technical Digest 1983 IEEE Int. Solid State Circuits Conf., pp. 104–105, 201, 1983.
187. G.A. Garrettson and A.P. Neukermans, “X-ray lithography,” Hewlett-Packard J., pp. 14–17, Aug. 1982.
188. “The x-ray stepper heads for the VLSI production line,” Electronics, pp. 41–44, Mar. 10, 1986.
189. J. Lyman, “It's a three-way race in x-ray lithography,” Electronics, pp. 46–49, Mar. 17, 1986.
190. C.L. Cohen, “Japan kicks off x-ray fabrication project,” Electronics, vol. 44, p. 44, Aug. 7, 1986.
191. M. Miyake et al. (NTT), “Subhalf-micrometer p-channel MOSFET's with 3.5-nm gate oxide fabricated using x-ray lithography,” IEEE Electron Device Lett., vol. EDL-8, no. 6, pp. 266–268, June 1987.
192. C.L. Cohen, “NEC draws 0.2-micron lines with x-rays,” Electronics, p. 34, Oct. 29, 1987.
193. G.E. Fuller, “Optical lithography status,” Solid State Technol., vol. 30, no. 9, pp. 113–118, Sept. 1, 1987.
194. C. Stedman, “Excimer-laser stepper, Report IBM, AT&T order GCA prototype,” Electronic News, p. 45, 47, Monday, June 22, 1987. See also B. Santo, “SRC deep-UV litho. effort hit by funding problems,” Electronic News, p. 45, 47, June 22, 1987.
195. For a recent development on photoresist and earlier technical references, see K.J. Orvek, W.C. Cunningham, Jr., and J.C. McFarland, “An organosilicon photoresist for use in excimer laser lithography,” in Technical Digest of 1987IEDM, paper 32.5, pp. 929–932, Dec. 1987.
196. J. Fallon and B. Santo, “IBM orders compact synchrotron,” Electronic News, p. 45, June 22, 1987.
197. J. Robertson, “IBM to develop. 0.25-micron ASIC gate array,” Electronic News, p. 25, June 13, 1988. For a recent development, see “IBM claims X-ray litho advance, fully-scaled ′0.25 μm' NMOS ICs at for exposure levels reported,” Electronic News, p. 38, Sept. 12, 1988.
198. See Electronics Week, p. 18, Apr. 15, 1985; “IBM facility's chip research progressing,” Computer World, p. 88, Apr. 22, 1985; “IBM works toward 16M-Bit Ram,” Mini-Micro Systems, July 1985. All of these three news releases stated that IBM Research employed a 0.5 micron aluminum metal NMOS electric beam technology to produce chips with 16M-bit RAM with 8.5 square micron cell area and 100 000 logic elements with 1700 MOSFETs per 100 x 100 square micron area.
199. B. Santo, “Say IBM signs Grumman for E-beam mfg.,” Electronic News, p. 38, Dec. 1, 1986. (This reported the IBM order of 40–50 direct-write electron beam systems.)
200. “IBM researchers build ULSI devices,” Electronics, vol. 60, no. 17, p. 110, Aug. 20, 1987.
201. “Getting tight in Yorktown Heights,” Electronic News, p. 29, Aug. 17, 1987. For a later account and photograph of the electron beam lithography machine, see J.A. Armstrong, “Solid state technology and the computer: 40 years later, small is still beautiful,” Solid State Techno!., pp. 81–83, Dec. 1987.
202. G.A. Sai-Halasz et al., “Experimental technology and characterization of self-aligned 0.1μm-gate-length low-temperature operation NMOS devices,” in Technical Digest of IEDM87, paper 16.5, pp. 397–400, Dec. 1987.
203. M. Murphy and L. Morgenthaler, “Why chips will soon kill off disk drives,” Electronic Business, pp. 74–78, Nov. 1, 1987.
204. E.W. Pugh, Memories That Shaped an Industry-Decisions Leading to IBM System/360. Cambridge, MA; The MIT Press, 1984.
205. For the 1946 von Neumann prophecy, see p. 34 of G. Bell and A. Newell, Computer Structures: Readings and Examples. New York, NY: McGraw-Hill, 1971.
206. H.Z. Bpgert, “FERRAM: the memory the market always wanted,” Dataquest Newsletter, Dataquest, Inc.,]an. 1988.
207. This 1-percent assumption strongly depends on application and CPU architecture. There are many detailed studies in recent years [97].
208. For CMOS development history, see R.D. Davies, “The case for CMOS,” IEEE Spectrum, vol. 20, no. 10, pp. 26–32, Oct. 1983 and the following articles [209]-[214].
209. B.C. Cole, “CMOS memories replacing n-MOS in megabit storage chips,” Electronics Week, pp. 53–61, Nov. 26, 1984.
210. B.C. Cole, “CAD, CMOS, and VLSI are changing analog world,” Electronics, pp. 35–39, Dec. 23, 1985.
211. Y. Nishi, “Direction of VLSI CMOS technology,” Hewlett-Packard J., pp. 24–25, June 1987.
212. R. Wilson, “CMOS VLSI sets the direction for new ICs,” Computer Design, pp. 79–91, Dec. 1987.
213. For a latest report on optical submicron technology for fabricating CMOS, see “0.25 μm CMOS technology using p + polysilicon gate PMOSFET,” in Technical Digest of 1987 IEDM, paper 15.5, pp. 367–370, Dec. 1987, and other articles in this digest. The readers should note that the so-called CMOS DRAM chip employs the one-transistor one-capacitor Dennard NMOS DRAM cell for the memory bits and the CMOS inverter gate is used only for peripheral drivers while a SRAM chip uses CMOS for both the six-transistor bistable flip-flop memory bit [134] as well as the peripheral drivers. The commonly used description 'CMOS DRAM,' in trade releases and engineering articles could be misleading since it could be interpreted as to mean that the memory cell is made of CMOS which is not.
214. “CMOS overtakes NMOS: ICE report,” Electronic News, p. 28, Mar. 14, 1988. See also the Feb. 4, 1988, issue of the Electronics magazine, vol. 61, no. 3, pp. 55–69, which discussed the question of BICMOS as the next technology driver and the production efforts of several American companies (Tl, National, LSI Logic, AMCC-American Micro Circuit Corp., and Saratoga).
215. The integrated bipolar-mosfet (BIMOS) cell was first used by C.T. Sah in his 1961 SCT (Surface-controlled Tetrode) experiments [77], [81] which were patented in Sah's two patents [78], [80]. The cross-sectional view of the structure used by Sah is given in the second patent of Sah [80] and also the 1963 McGraw-Hill Yearbook [79] shown in Fig. 6(c).
216. For additional accounts of recent developments on BIMOS and BICMOS, see C.L. Cohen,” Cells combine CMOS, bipolar transistors,” Electronics Week, p. 17–18, Nov. 5, 1984, and the following references [217]-[220].
217. L. Waller, “Behind Motorolas silence: ambitious product plans, company unwraps a slew of products, commits to BIMOS,” Electronics, pp. 18–19, Nov. 25, 1985.
218. E. Connolly, “BiMOS devices give designers the best of two worlds,” and “How BiMOS reduces delays,” Computer Design, pp. 22–25, June 1, 1987.
219. C.L. Cohen, “Here comes a 256-k SRAM (1-μm BiCMOS) and it's from Fairchild,” Electronics, pp. 34–35, June 11, 1987.
220. S. Weber, “Tl to roll out its first family of products made with BiCMOS,” Electronics, pp. 81–82, Oct. 1, 1987.
221. P.H. Solomon, “A comparison of semiconductor devices for highspeed logic,” Proc. IEEE, vol. 70, no. 5, pp. 489–509, May 1982.
222. F. Gaensslen and D.E. Nelsen, “Solid-state devices-low temperature device operation,” in Technical Digest ofIEDM-87, pp. 379-408, IEEE Publication Catalog No. 87CH2515–5.
223. L.M. Terman, 1967 (unpublished) [97].
224. A system level experiment was performed by Digital Equipment Corporation researchers in which a 3-micron 2-chip. 32-bit CMOS based CPU (DEC part DCJ11) was cooled from 300 to 77K. A factor of two improvement in the maximum clock frequency was observed, from 20 to 40 MHz. See G. Gildenblat, L. Colonna-Romano, D. Lau, and D.E. Nelsen, “Investigation of cryogenic CMOS performance,” in Technical Digest of Int. Electron Device Meeting, pp. 268-271, Dec. 1-4, 1985. IEEE Publication Catalog No. 85CH2252–5.
225. H. Morkoc and P.M. Solomon, “The HEMT: a superfast transistor,” IEEE Spectrum, pp. 28–35, Feb. 1984.
226. P.M. Solomon and H. Morkoc, “Modulation doped GaAs/ AIGaAs heterojunction field effect transistors (MODFETs): Ultra high speed devices for super computer,” IEEE Trans. Electron Devices, vol. ED-31, pp. 1015–1028, 1984.
227. For a recent account on GaAs devices in Japan, see T.E. Bell, “Japan reaches beyond silicon,” IEEE Spectrum, pp. 46–52, Oct. 1985.
228. J.W. Goodman, F.I. Leonberger, S.-Y. Kung, and R.A. Athale, “Optical interconnections for VLSI systems,” Proc. IEEE, vol. 72, no. 7, pp. 850–866, July 1984. See also the whole issue which is devoted to optical electronics and integrated optics.
229. B.Y. Tsaur et al., “Low dislocation density GaAs epilayers grown on Ge-coated Si substrates by means of lateral epitaxial growth,” Appl. Phy. Lett., vol. 41, no. 4, pp. 347–349, Apr. 1982.
230. R.M. Fletcher, D.K. Wagner, and J.M. Ballantyne, “GaAs light-emitting diodes fabricated on Ge-coated Si substrates,” Appl. Phys. Lett., vol. 44, pp. 967–969, 1984.
231. T.H. Windhorn, G.M. Metze, B.-Y. Tsaur, and J.C.C. Fan, “AIGaAs double-heterostructure diode lasers fabricated on a monolithic GaAs/Si substrate,” Appl. Phys. Lett., vol. 45, pp. 309–311, 1984.
232. T. Windhorn and G.M. Metz, “Room temperature operation of GaAs/AIGaAs diode lasers fabricated on a monolithic GaAs/Si substrate,” Appl. Ehys. Lett., vol. 47, pp. 1031–1033, 1985.
233. R. Fischer et al., “GaAs/AIGaAs MOSFETs grown directly on (100) silicon,” Electronics Letters, vol. 20, pp. 945–947, 1984.
234. R. Fischer et al., “Monolithic integration of GaAs/AIGaAs modulation doped field effect transistors and N-metal oxide semiconductor silicon circuits,” Appl. Phys. Lett, vol. 47, pp. 983–985, 1985.
235. H.K. Choi, B.-Y. Tsaur, G.M. Metze, G.W. Turner, and]. C.C. Fan, “GaAs MESFETs fabricated on monolithic GaAs/Si substrates,” IEEE Electron Devices Lett., vol. EDL-5, pp. 207–208, 1984.
236. J. Nonake, M. Akiyama, Y. Kawarada, and K. Kaminiski, “Fabrication of GaAs MESFET ring oscillator on MOCVD grown on GaAs/Si(100) substrate,” Japan J. Appl. Phys., vol. 23, pp. L919-L921, 1984.
237. R. Fischer et al., “GaAs/AIGaAs heterojunction bipolar transistors on Si substrates,” in Digest of Int. Electron Devices Meeting, pp. 332-335, Dec. 2-4, 1985. IEEE Catalog No. 85CH2252–5.
238. R. Fischer et al., “CaAs bipolar transistors grown on (100) Si substrate by molecular beam epitaxy,” Appl. Phys. Lett, vol. 47, pp. 397–399, 1985.
239. A.Y. Cho, “Recent advances in GaAs on Si,” in Technical Digest, IEDM-87, pp. 901-904, Dec. 1987. IEEE Publication No. 87-CH2515–5.
240. H. Shichijo and R.J. Matyi, “GaAs-on-Silicon integrated circuits: savior for GaAs? Or for Si?,” in Technical Digest, IEDM-87, pp. 88-91, Dec. 1987. IEEE Publication No. 87-CH2515–5.
241. “Tl claims Si, GaAs linked on chip,” Electronic News, p. 20, July 4, 1988. A cross-sectional view is given of a GaAs MESFET in a GaAs epitaxy layer grown on a 3°-off >100> Si substrate and integrated with a twin-well Si CMOS by R.J. Matyi and H. Shichijo.
242. H. Shichijo is another former graduate student at the University of Illinois who took my semiconductor physics course, EE/Physics 435, in the spring semester of 1977. He was one of the best students of that class.
243. Data released by DARPA (Defense Advanced Research Project Agency), see R. Beresford, “Military VLSI technology,” VLSI Design, pp. 46–54, Apr. 1984.
244. Progresses are being made in the last two years due to a $60M U.S. government funding, for example, see H. Bierman, “Move over silicon! Here comes GaAs making complex devices starts to get easier,” Electronics, pp. 39–44, Dec. 2, 1985, and the following references [245], [246].
245. T. Naegele, “U.S. GaAs makers move to catch up,” Electronics, p. 17, Mar. 17, 1986. See however, [246].
246. A. Wing, “GaAs startups struggle with high costs, low densities and sparse yield,” Electronic News, vol. 32, no. 1549, p. 1, Mar. 24, 1986.
247. “Rockwell breaks 1% yield barrier for GaAs 16kbit RAM,” Electronics, p. 162, Jan. 7, 1988.
248. L. Waller, “Commercial quantities of LSI GaAs are finally here,” Electronics, pp. 48–49, Sept. 17, 1987.
249. W.R. Iversen, “Cray is still using GaAs-but not its own,” Electronics, p. 49, Sept. 17, 1987. See also [265].
250. A. Pollack, “Gallium arsenide chips making research gains,” The New York Times, Sunday, Oct. 25, 1987.
251. “Kopin offers GaAs-on-Silicon wafers for research,” Electronic News, p. 39, Oct. 19, 1987.
252. V. Rice, “The making of a military GaAs market,” Electronic Business, pp. 46–50, July 15, 1987.
253. J. Lineback, “Hybrid (GaAs-Si) amp(lifier) has double the AGC of silicon only,” Electronics, pp. 170–172, Jan. 7, 1987.
254. C.T. Sah, “Models and experiments on degradation of oxidized silicon,” in Proceeding of IFOS-87, also in Applied Surface Science, vol. 30, pp. 311–12, 1987.
255. C.T. Sah, “VLSI device reliability modeling,” in Proceedings of 1987 Int. Symp. on VLSI Technology, Systems and Applications, pp. 153-162, May 13–15, 1987.
256. For a review of the fundamental physics and analysis of the published data related to failure of silicon dioxide film on silicon, see [87].
257. C.T. Sah, “Hydrogenation and dehydrogenation of shallow acceptors and donors in Si: fundamental phenomena and survey of the literature,” in Properties of SILICON. London, England: INSPEC, The Institution of Electrical Engineers, section 17.16, pp. 584-604, May 1988. Available from INSPEC Dept., IEEE Service Center, 455 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855–1331.
258. C.T. Sah et al., “Hydrogenation and dehydrogenation of shallow acceptors and donors in Si: kinetic rate data,” in Properties of SILICON. London, England: INSPEC, The Institution of Electrical Engineers, section 17.17, pp. 604-613, May 1988. Available from INSPEC Dept, IEEE Service Center, 455 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855–1331.
259. For a pedestrain account, see W.R. Iversen, “Model may help solve chip-reliability problem,” Electronics, vol. 59, no. 12, pp. 21–24, Mar. 24, 1986.
260. Semiconductor Research Corporation, “Industrial Mentor Handbook,” ch. Ill, pp. 9–17, SRC Publication S87011, July 1987.
261. M. Eleccion, “The electronic watch,” IEEE Spectrum, vol. 10, no. 4, pp. 24–32, Apr. 1973.
262. J. Robertson, “SIA: DRAM Consortium are eyed,” Electronic News, p. 6, Sept. 19, 1988; also J. Titta, “Drumming up DRAM support,” Computerworld, p. 8, Oct. 31, 1988.
263. Electronic News, p. 36, Oct. 3, 1988; also A.M. Hayashi, “How Micron is marching through the DRAM minefield,” Electronic Business, pp. 42–46, June 15, 1988.
264. “ECLvs. GaAschips:Lettheclock-speedgamesbegin,” f/ectronic Business, pp. 103–104, June 15, 1988.
265. For recent Cray-3 problem due to GaAs chips, see J. Bailey and R. Gibson, “Cray stumbles with new supercomputers,” Wall Street J., p. 1, Oct. 26, 1988; J.S. Bozman, “Cray revenue slips, Y-MP, Cray-3 woes hurt supercomputer firm,” Computerworld, p. 6, Oct. 31, 1988; “Snags in GaAs circuits hit Cray 3; Charge: $10M,” Electronic News, p. 14, Oct. 31, 1988.
266. “IBM may go to GaAs for′90s CPUs: Study,” Electronic News, p. 46, Sept. 12, 1988.