A Study of Deep-Submicron MOSFET Scaling Based on Experiment and Simulation

IEEE Transactions on Electron Devices

Volumn 42, Issue 4, 1995, Pages 669-677

  Hu, Hang ^a   Jacobs, Jarvis B ^a   Su, Lisa T ^a   Antoniadis, Dimitri A ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; FUNCTIONS; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; SET THEORY; STATISTICAL METHODS; TRANSCONDUCTANCE;

CHANNEL DOPING PROFILE; CHANNEL EFFECT; CHANNEL PARAMETERS; DEEP SUBMICRON MOSFET SCALING; DEVICE PARAMETERS; DRAIN INDUCED BARRIER LOWERING; JUNCTION ABRUPTNESS; PARASITIC RESISTANCE; POWER COEFFICIENT; THRESHOLD VOLTAGE;

MOSFET DEVICES;

EID: 0029289875     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.372070     Document Type: Article

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