HIERARCHIAL CIRCUIT EXTRACTION WITH DETAILED PARASITIC CAPACITANCE.

Proceedings - Design Automation Conference

Volumn , Issue , 1983, Pages 337-345

  Tarolli, Gary M ^a   Herman, William J ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT EXTRACTION; EXTRACTION ALGORITHM; HIERARCHICAL EXTRACTION ALGORITHM; INTERCONNECT VERIFIER (IV); IV MOS LAYOUT VERIFICATION PROGRAM; PARASITIC CAPACITANCE;

INTEGRATED CIRCUITS;

EID: 0020603675     PISSN: 01467123     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)