Modular design of communication node prototypes

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1997, Pages 170-175

  D'Angelo, Sergio ^a   Mantoani, Lauro ^a   Mazzei, Riccardo P G ^a   Russo, Stefania ^a   Sechi, Giacomo R ^a  

^a Istituto di Fisica Cosmica e Tecnologie Relative   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; ELECTRIC NETWORK TOPOLOGY; LOGIC CIRCUITS; LOGIC GATES; PARALLEL PROCESSING SYSTEMS; RAPID PROTOTYPING;

COMMUNICATION NODE PROTOTYPES; FIELD PROGRAMMABLE GATE ARRAYS; MACRO LIBRARY; MASSIVELY PARALLEL SYSTEMS; PROCESSING ELEMENTS; RESOURCE SHARING;

MACROS;

EID: 0030697724     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)