A 0.4-4Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 88-91

  Chang, Kun Yung Ken ^a   Wei, Jason ^a   Li, Simon ^a   Li, Yingxuan ^a   Donnelly, Kevin ^a   Huang, Charlie ^b   Sidiropoulos, Stefanos ^c  

^a RAMBUS INC   (United States)

^b T RAM Inc   (United States)

^c Aeluros Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENT REGULATORS; INTEGRATED CIRCUIT MANUFACTURE; JITTER; OPERATIONAL AMPLIFIERS; PHASE LOCKED LOOPS; TELECOMMUNICATION LINKS; VARIABLE FREQUENCY OSCILLATORS;

DUAL-LOOP PHASE LOCKED LOOPS; PHASE FREQUENCY DETECTOR; QUAD TRANSCEIVER CELL;

TRANSCEIVERS;

EID: 0242526937     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

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