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Volumn 32, Issue 4, 1997, Pages 514-520

NRZ timing recovery technique for band-limited channels

Author keywords

Decision feedback equalizers phase detection; Phase locked loops

Indexed keywords

BANDWIDTH; COMMUNICATION CHANNELS (INFORMATION THEORY); EQUALIZERS; INTERSYMBOL INTERFERENCE; PHASE LOCKED LOOPS; PULSE MODULATION; SIGNAL FILTERING AND PREDICTION; TIMING CIRCUITS;

EID: 0031123768     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.563672     Document Type: Article
Times cited : (28)

References (9)
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  • 3
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    • Soyuer, M.1    Ainspan, H.2
  • 5
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    • A monolithic 156 Mb/s clock and data-recovery PLL circuit using the sample-and-hold technique
    • Feb.
    • N. Ishihara and Y. Akazawa, "A monolithic 156 Mb/s clock and data-recovery PLL circuit using the sample-and-hold technique," in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 110-111.
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    • Ishihara, N.1    Akazawa, Y.2
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    • AFC tracking algorithms
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.