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Volumn 143, Issue 5, 1996, Pages 282-286

Asynchronous FPGA architectures

Author keywords

Architectures; Asynchronous circuits; Field programmable gale arrays

Indexed keywords

COMPUTER CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; PROGRAM PROCESSORS;

EID: 0030235194     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:19960655     Document Type: Article
Times cited : (40)

References (16)
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    • Sutherland, I.E.1
  • 3
    • 33746122927 scopus 로고
    • Implementing self-timed systems: Comparison of configurable logic arrays with full custom circuits
    • Abingdon EE&CS Books, chap. 6.3
    • OLDFIELD, J., and KAPPLER, C: 'Implementing self-timed systems: comparison of configurable logic arrays with full custom circuits' in 'FPGAs: international workshop on Field programmable logic and applications' (Abingdon EE&CS Books, 1991), chap. 6.3
    • (1991) FPGAs: International Workshop on Field Programmable Logic and Applications
    • Oldfield, J.1    Kappler, C.2
  • 4
    • 0027641441 scopus 로고
    • Using FPGAs to implement self-timed systems
    • BRUNVAND, E.: 'Using FPGAs to implement self-timed systems', J. VLSI Signal Process., 1993, 6, (2), pp. 173-190
    • (1993) J. VLSI Signal Process. , vol.6 , Issue.2 , pp. 173-190
    • Brunvand, E.1
  • 6
    • 4644371793 scopus 로고
    • Hazard-free implementation of the self-timed cell set for the Xilinx 4000 series FPGA
    • U.C.Davis
    • MAHESWARAN, K., and AKELLA, V.: 'Hazard-free implementation of the self-timed cell set for the Xilinx 4000 series FPGA'. Technical report, U.C.Davis, 1994
    • (1994) Technical Report
    • Maheswaran, K.1    Akella, V.2
  • 8
    • 33746171256 scopus 로고
    • A highly parallel FPGA-based machine and its formal verification
    • University of Strathclyde
    • SHAW, P., and MILNE, G.: 'A highly parallel FPGA-based machine and its formal verification'. Technical report HDV-28-93, University of Strathclyde, 1993
    • (1993) Technical Report HDV-28-93
    • Shaw, P.1    Milne, G.2
  • 12
  • 14
    • 33746114433 scopus 로고
    • The King's Buildings, TTC, Edinburgh EH9 3JL, UK
    • Algotronix Ltd.: 'CAL1024 datasheet'. The King's Buildings, TTC, Edinburgh EH9 3JL, UK, 1991
    • (1991) CAL1024 Datasheet
  • 16
    • 0024070224 scopus 로고
    • Q-Modules: Internally clocked delay-insensitive modules
    • ROSENBERGER, F.U., MOLNAR, C.E., CHANEY, T.J., and FANG, T.: 'Q-Modules: internally clocked delay-insensitive modules', IEEE Trans., 1988, C-37, (9), pp. 1005-1018
    • (1988) IEEE Trans. , vol.C-37 , Issue.9 , pp. 1005-1018
    • Rosenberger, F.U.1    Molnar, C.E.2    Chaney, T.J.3    Fang, T.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.