Cell designs for self-timed FPGAs

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2001, Pages 175-179

  Traver, Cherrice ^a   Reese, Robert B ^b   Thornton, Mitch A ^b  

^a UNION COLLEGE   (United States)

^b MISSISSIPPI STATE UNIVERSITY   (United States)

Author keywords

Asynchronous; Programmable; Self timed

Indexed keywords

DELAY CIRCUITS; ESTIMATION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; LOGIC GATES; SIGNAL ENCODING; TABLE LOOKUP;

PHASED LOGIC SYSTEMS; SELF TIMED CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0034776527     PISSN: 10630988     EISSN: None     Source Type: Journal    
DOI: 10.1109/ASIC.2001.954693     Document Type: Article

References (18)

1. Scanning the technology: Applications of asynchronous circuits
2. Phased logic: Supporting the synchronous design paradigm with delay-insensitive circuitry
3. Phased logic: A design methodology for delay-insensitive synchronous circuitry
4. Synthesis and simulation of phased logic systems
5. Four state asynchronous architectures
6. Efficient self-timing with level-encoded 2-phase dual-rail (LEDR)
7. A self clocked FPGA for general purpose logic emulation
8. Asynchronous design using commercial HDL synthesis tools
9. A theory of asynchronous circuits
10. A design of a fast and area efficient mult-input muller C-element
11. Micropipelines
12. Self-timed iteration
13. An FPGA for implementing asynchronous circuits
14. CMOS circuit design of threshold gates with hysteresis
15. An asynchronous 2-D discrete cosine transform chip