Highly pipelined asynchronous FPGAs

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn 12, Issue , 2004, Pages 133-142

  Teifel, John ^a   Manohar, Rajit ^a  

^a Cornell University ^*  (United States)

Author keywords

Asynchronous circuits; Concurrency; Correctness by construction; Pipelining; Programmable logic

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; BENCHMARKING; COMPUTATIONAL METHODS; DATA REDUCTION; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; PROGRAMMABLE LOGIC CONTROLLERS;

ASYNCHRONOUS CIRCUITS; CONCURRENCY; CORRECTNESS BY CONSTRUCTION; PIPELINING; PROGRAMMABLE LOGIC; ROUTING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 2442476371     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/968280.968300     Document Type: Conference Paper

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