Ultrathin Body Silicon on Insulator Transistors for 22 nm Node and Beyond

Engineering Materials

Volumn , Issue , 2011, Pages 155-168

  Poiroux, T ^a   Andrieu, F ^a   Weber, O ^a   Fenouillet Beranger C ^a   Buj Dufournet, C ^a   Perreau, P ^a   Tosti, L ^a   Brevard, L ^a   Faynot, O ^a  

^a CEA LETI   (France)

Author keywords

Drain Induce Barrier Lowering; Line Edge Roughness; Metal Gate; Static Noise Margin; Threshold Voltage

Indexed keywords

COMPUTER CIRCUITS; SILICON ON INSULATOR TECHNOLOGY;

BARRIER LOWERING; DRAIN INDUCE BARRIER LOWERING; ELECTROSTATIC CONTROL; LINE EDGE ROUGHNESS; METAL-GATE; PERFORMANCE; SILICON-ON-INSULATOR TRANSISTORS; SILICONON-INSULATOR TECHNOLOGY (SOI); STATIC NOISE MARGIN; ULTRATHIN BODY SILICON-ON-INSULATOR;

THRESHOLD VOLTAGE;

EID: 85126678638     PISSN: 16121317     EISSN: 18681212     Source Type: Book Series    
DOI: 10.1007/978-3-642-15868-1_8     Document Type: Chapter

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