Fully depleted silicon-on-insulator with back bias and strain for low power and high performance applications

2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010

Volumn , Issue , 2010, Pages 59-62

  Andrieu, F ^a   Weber, O ^a   Baudot, S ^b   Fenouillet Beranger C ^a   Rozeau, O ^a   Mazurier, J ^a   Perreau, P ^a   Eymery, J ^b   Faynot, O ^a  

^a CEA LETI   (France)

^b CEA GRENOBLE   (France)

Author keywords

MIS devices; Silicon on insulator technology; Strain

Indexed keywords

BACK BIAS; BULK TECHNOLOGIES; BURIED OXIDES; DYNAMIC PERFORMANCE; ELECTROSTATIC CONTROL; EMBEDDED SIGE SOURCE/DRAIN; FULLY DEPLETED SILICON-ON-INSULATOR; HIGH EFFICIENCY; HIGH PERFORMANCE APPLICATIONS; IDEAL SOLUTIONS; LOW POWER; LOW POWER APPLICATION; METAL OXIDE SEMICONDUCTOR; ON STATE CURRENT; POWER MANAGEMENT TECHNIQUES; SOURCE BIASING; SRAM STABILITY; STRAINED-SOI; ULTRATHIN BODY;

ELECTROSTATIC DEVICES; ENERGY MANAGEMENT; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; MIS DEVICES; TECHNOLOGY;

SILICON ON INSULATOR TECHNOLOGY;

EID: 77955634148     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2010.5510295     Document Type: Conference Paper

References (18)

1. S. E. Thompson, R. S. Chau, T. Ghani, K. Mistry, S. Tyagi, M. Bohr, "In Search of "Forever", continued transistor scaling one new material at a time", IEEE Transactions on Electron Devices, 18, 1, p. 26, 2005.
2. M. Ieong, B. Doris, J. Kedzierski, K. Rim, M. Yang, "Silicon Device Scaling to the Sub-10-nm Regime", Science, 306, p. 2057, 2004.
3. V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J.M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J.L. Autran and S. Deleonibus, "Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack", IEDM Tech Dig., pp. 61-4, 2007.
4. F. Andrieu, O. Weber, J. Mazurier, O. Thomas, J-P. Noel, C. Fenouillet- Béranger, J-P. Mazellier, P. Perreau, T. Poiroux, Y. Morand, T. Morel, S. Allegret, V. Loup, S. Barnola, F. Martin, J-F. Damlencourt, I. Servin, M. Cassé, X. Garros, O. Rozeau, M-A. Jaud, G. Cibrario, J. Cluzel, A. Toffoli, F. Allain, R. Kies, D. Lafond, V. Delaye, C. Tabone, L. Tosti, L. Brévard, P. Gaud, V. Paruchuri, K.K. Bourdelle, W. Schwarzenbach, O. Bonnin, B-Y. Nguyen, B. Doris, F. Boeuf, T. Skotnicki, O. Faynot, "Low Leakage and Low Variability Ultra-Thin Body and Buried Oxide (UT2B) SOI Technology for 20nm Low Power CMOS and Beyond", accepted to the Symposium of VLSI Technology, 2010.
5. C. Fenouillet-Beranger, P. Perreau, L. Pham-Nguyen, S. Denorme, F. Andrieu, L. Tosti, L. Brevard, O. Weber, S. Barnola, T. Salvetat, X. Garros, M. Cassé, C. Leroux, B. Le-Gratiet, F. Baron, M. Gattefait, Y. Campidelli, F. Abbate, C. Perrot, C. de-Buttet, R. Beneyton, L. Pinzelli, F. Leverd, P. Gouraud, M. Gros-Jean, A. Bajolet, C. Mezzomo, C. Leyris, S. Haendler, D. Noblet, R. Pantel, A. Margain, C. Borowiak, E. Josse, N. Planes, D. Delprat, F. Boedt, K. Bourdelle, B.Y. Nguyen, F. Boeuf, O. Faynot, T. Skotnicki, « Hybrid FDSOI/Bulk high-k/Metal gate platform for Low Power (LP) multimedia technology », IEDM Tech Dig., 2009.
6. B. Doris, Y.H. Kim, B.P. Linder, M. Steen, V. Narayanan, D. Boyd, J. Rubino, L. Chang, J. Sleight, A. Topol, E. Sikorski, L. Shi, L. Wong, K. Babich, Y. Zhang, P. Kirsch, J. Newbury, J. F. Walker, R. Carruthers, C. D'Emic, P. Kozlowski, R. Jammy, K. W. Guarini, M. Leong, "High Performance FDSOI CMOS Technology with Metal Gate and High-k", Symposium of VLSI Technology Dig., p. 214, 2005.
7. Z. Krivokapic, W. Maszara, F. Arasnia, E. Paton, Y. Kim, L. Washington, E. Zhao, J. Chan, J. Zhang, A. Marathe, M-R. Lin, "High Performance 25nm FDSOI Devices with Extremely Thin Silicon Channel", IEDM Tech. Dig., p. 131, 2003.
8. C. Fenouillet-Beranger, L. Pham Nguyen, P. Perreau, S. Denorme, F. Andrieu, O. Faynot, L. Tosti, L. Brevard, C. Buj, O.Weber, C. Gallon, V. Fiori, F. Boeuf, S. Cristoloveanu, T. Skotnicki, "Ultra compact FDSOI transistors (including Strain and orientation) processing and performance", ECS Transaction, 2009.
9. S. Baudot, F. Andrieu, O. Faynot, J. Eymery, "Electrical and diffraction characterization of short and narrow MOSFETs on Fully Depleted strained Silicon-On-Insulator (sSOI)", Solid State Electronics, to be published in 2010.
10. F. Andrieu, C. Fenouillet-Beranger, O. Weber, S. Baudot, C. Buj, J.-P. Noel, O. Thomas, O. Rozeau, P. Perreau, L. Tosti, L. Brevard, O. Faynot, "Ultrathin Body and BOX SOI and sSOI for Low Power Application at the 22nm technology node and below", invited talk at SSDM, 2009.
11. S. Baudot, F. Andrieu, O. Weber, P. Perreau, J.F. Damlencourt, S. Barnola, T. Salvetat, L. Tosti, L. Brévard, D. Lafond, J. Eymery, O. Faynot, "Fully-Depleted Strained Silicon-On-Insulator p-MOSFETs with Recessed and Embedded Silicon-Germanium Source/Drain", to be published in 2010.
12. 2/TiN gate stack down to 15nm gate length", IEEE SOI Conference, p. 223-5, 2005.
13. T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, S. Takagi, "(110)-Surface Strained-SOI CMOS Devices", IEEE Transaction of Electron Devices, 52, 3, p.367, 2005.
14. T. Signamarcheix, F. Andrieu, B. Biasse, M. Cassé, A-M. Papon, E. Nolot, B. Ghyselen, O. Faynot and L. Clavelier, "Fully depleted silicon on insulator MOSFETs on (110) surface for hybrid orientation technologies", to be published in 2010.
15. C. Fenouillet-Beranger, O. Thomas, P. Perreau, J-P. Noel, A. Bajolet, S. Haendler, L. Tosti , S. Barnola, R. Beneyton, C. Perrot, C. de Buttet, F. Abbate, F. Baron, B. Pernet, Y. Campidelli, L. Pinzelli, P. Gouraud, M. Cassé, C. Borowiak, O. Weber, F. Andrieu, K.K. Bourdelle, B.Y. Nguyen, F. Boedt, S. Denorme, F. Boeuf, O. Faynot, T. Skotnicki, « Efficient Multi-VT FDSOI technology with UTBOX for low power circuit design », accepted to the Symposium of VLSI Technology, 2010.
16. A. Vandooren, A.V.Y. Thean, Y. Du, I. To, J. Hugues, T. Stephens, M. Huang, S. Egley, M. Zavala, K. Sphabmixav, A. Barr, T. White, S. Samavedam, L. Mathew, J. Schaeffer, D. Trivoso, M. Rossow, D. Roan, D. Pham, R. Rai, B.-Y. Nguyen, B. White, M. Orlowski, A. Duvallet, T. Dao, J. Mogab, "Mixed-signal performance of sub-100nm fully-depleted SOI devices with metal gate, high-K (HfO2) dielectric and elevated Source/Drain extensions", IEDM Tech. Dig., p. 978, 2003.
17. O. Weber, O. Faynot, F. Andrieu, C. Buj-Dufournet, F. Allain, P. Scheiblin, J. Foucher, N. Daval, D. Lafond, L. Tosti, L. Brevard, O. Rozeau, C. Fenouillet-Beranger, M. Marin, F. Boeuf, D. Delprat, K. Bourdelle, B.Y. Nguyen, S. Deleonibus, «High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding», IEDM Tech Dig., pp. 641-4, 2008.
18. K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, J. Kuss, D. Shahrjerdi, L. F. Edge, A. Kimball, S. Kanakasabapathy, K. Xiu, S. Schmitz, A. Reznicek, T. Adam, H. He, N. Loubet, S. Holmes, S. Mehta, D. Yang, A. Upham, S.-C. Seo, J. L. Herman, R. Johnson, Y. Zhu, P. Jamison, B. S. Haran, Z. Zhu, L. H. Vanamurth, S. Fan, D. Horak, H. Bu, P. J. Oldiges, D. K. Sadana, P. Kozlowski, D. McHerron, J. O'Neill, B. Doris, "Extremely Thin SOI (ETSOI) CMOS with Record Low Variability for Low Power System-on-Chip Applications", IEDM Tech Dig., p. 49, 2009.