Efficient multi-VT FDSOI technology with UTBOX for low power circuit design

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2010, Pages 65-66

  Fenouillet Beranger, C ^a,b   Thomas, O ^b   Perreau, P ^a,b   Noel, J P ^b   Bajolet, A ^a   Haendler, S ^a   Tosti, L ^b   Barnola, S ^b   Beneyton, R ^a   Perrot, C ^a   De Buttet, C ^a,b   Abbate, F ^a   Baron, F ^a   Pernet, B ^a   Campidelli, Y ^a   Pinzelli, L ^a   Gouraud, P ^a   Casse M ^b   Borowiak, C ^a   Weber, O ^b   Andrieu, F ^b   Bourdelle, K K ^c   Nguyen, B Y ^c   Boedt, F ^c   Denorme, S ^a   Boeuf, F ^a   Faynot, O ^b   Skotnicki , T ^a   more..

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

^c PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC PERFORMANCE; LEAKAGE REDUCTION; LOW POWER APPLICATION; LOW-POWER CIRCUIT DESIGN; RING OSCILLATOR; STATIC POWER;

INTEGRATED CIRCUIT MANUFACTURE; OSCILLATORS (ELECTRONIC); STATIC RANDOM ACCESS STORAGE; TECHNOLOGY;

VLSI CIRCUITS;

EID: 77957876619     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2010.5556118     Document Type: Conference Paper

References (6)

1. C. Fenouillet-Beranger etal, IEDM 2007, p. 267, .
2. JP.Noel et al, ESSDERC2009, p.137, .
3. Y. Morita, etal, VLSI 2008, p. 166, .
4. C.Fenouillet-Beranger, et al, IEDM 2009, p. 667, .
5. C.Fenouillet-Beranger, et al, ESSDERC 2009, p.89, .
6. JB.Yau, et al, VLSI-TSA 2009, p.84.