On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?

Proceedings - Real-Time Systems Symposium

Volumn 2018-December, Issue , 2019, Pages 495-505

  Hassan, Mohamed ^a,b  

^a UNIVERSITY OF GUELPH   (Canada)

^b INTEL CORPORATION   (United States)

Author keywords

DRAM; Latency Analysis; Memory; Predictability; Real Time Systems

Indexed keywords

DATA STORAGE EQUIPMENT; DYNAMIC RANDOM ACCESS STORAGE; INTERACTIVE COMPUTER SYSTEMS;

DYNAMIC RANDOM ACCESS MEMORY; INHERENT LIMITATIONS; LATENCY ANALYSIS; MEMORY CONTROLLER; PREDICTABILITY; REDUCED LATENCIES; STRINGENT REQUIREMENT; TIMING CONSTRAINTS;

REAL TIME SYSTEMS;

EID: 85061555818     PISSN: 10528725     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTSS.2018.00062     Document Type: Conference Paper

References (40)

1. O. Mutlu and L. Subramanian, "Research problems and opportunities in memory systems, " Supercomputing frontiers and innovations, 2014.
2. M. Hassan and H. Patel, "MCXplore: Automating the validation process of DRAM memory controller designs, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.
3. H. Kim, D. De Niz, B. Andersson, M. Klein, O. Mutlu, and R. Rajkumar, "Bounding memory interference delay in COTS-based multi-core systems, " in IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014.
4. H. Yun, R. Pellizzon, and P. K. Valsan, "Parallelism-Aware memory interference delay analysis for COTS multicore systems, " in IEEE Euromicro Conference on Real-Time Systems, 2015.
5. B. Akesson, K. Goossens, and M. Ringhofer, "Predator: a predictable SDRAM memory controller, " in IEEE/ACM international conference on Hardware/software codesign and system synthesis (CODES+ ISSS), 2007.
6. J. Reineke, I. Liu, H. D. Patel, S. Kim, and E. A. Lee, "PRET DRAM controller: Bank privatization for predictability and temporal isolation, " in IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (CODES+ ISSS), 2011.
7. L. Ecco and R. Ernst, "Improved DRAM timing bounds for teal-Time DRAM controllers with read/write bundling, " in Real-Time Systems Symposium, 2015, pp. 53-64.
8. L. Ecco, A. Kostrzewa, and R. Ernst, "Minimizing DRAM rank switching overhead for improved timing bounds and performance, " in Euromicro Conference on Real-Time Systems (ECRTS), 2016.
9. L. Ecco, S. Tobuschat, S. Saidi, and R. Ernst, "A mixed critical memory controller using bank privatization and fixed priority scheduling, " in IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 2014.
10. S. Goossens, B. Akesson, and K. Goossens, "Conservative open-page policy for mixed time-criticality memory controllers, " in Proceedings of the Conference on Design, Automation and Test in Europe. EDA Consortium, 2013, pp. 525-530.
11. H. Kim, D. Broman, E. A. Lee, M. Zimmer, A. Shrivastava, and J. Oh, "A predictable and command-level priority-based DRAM controller for mixed-criticality systems, " in Real-Time and Embedded Technology and Applications Symposium (RTAS), 2015, pp. 317-326.
12. M. Hassan, H. Patel, and R. Pellizzoni, "A Framework for Scheduling DRAM Memory Accesses for Multi-Core Mixed-Time Critical Systems, " in Real-Time and Embedded Technology and Applications Symposium (RTAS), 2015, pp. 307-316.
13. -, "PMC: A requirement-Aware DRAM controller for multi-core mixed criticality systems, " in ACM Transactions on Embedded Computing Systems (TECS), 2016.
14. J. Jalle, E. Quinones, J. Abella, L. Fossati, M. Zulianello, and F. J. Cazorla, "A dual-criticality memory controller (DCmc): Proposal and evaluation of a space case study, " in IEEE Real-Time Systems Symposium (RTSS), 2014.
15. M. Paolieri, E. Quiñones, F. J. Cazorla, and M. Valero, "An analyzable memory controller for hard real-Time CMPs, " Embedded System Letters (ESL), vol. 1, pp. 86-90, 2009.
16. Y. Li, B. Akesson, and K. Goossens, "Dynamic command scheduling for real-Time memory controllers, " in Euromicro Conference on Real-Time Systems (ECRTS), 2014, pp. 3-14.
17. Z. P. Wu, Y. Krish, and R. Pellizzoni, "Worst case analysis of DRAM latency in multi-requestor systems, " in Real-Time Systems Symposium (RTSS), 2013, pp. 372-383.
18. Y. Krishnapillai, Z. P. Wu, and R. Pellizoni, "ROC: A rank-switching, open-row DRAM controller for time-predictable systems, " in Euromicro Conference on Real-Time Systems (ECRTS), 2014.
19. P. K. Valsan and H. Yun, "MEDUSA: a predictable and highperformance DRAM controller for multicore based embedded systems, " in Cyber-Physical Systems, Networks, and Applications (CPSNA), 2015, pp. 86-93.
20. "JEDEC DDR3 SDRAM specifications jesd79-3d, " http://www.jedec.Org/standards-documents/docs/jesd-79-3d, accessed: 2018-09-12.
21. "Micron RLDRAM3 SDRAM part mt44k64m18rb 093e, " Micron Technology Inc. Accessed: 2018-09-12. [Online]. Available: https://www.micron.com/%7E/media/documents/products/data-sheet/dram/1,-d-, 125gb%5Fx18%5Fx36%5Frldram3.pdf
22. M. Hassan and R. Pellizzoni, "Bounding DRAM interference in COTS heterogeneous MPSoCs for mixed criticality systems, " in ACM SIGBED International Conference on Embedded Software (EMSOFT), 2018.
23. H. Yun, R. Mancuso, Z.-P. Wu, and R. Pellizzoni, "PALLOC: DRAM bank-Aware memory allocator for performance isolation on multicore platforms, " in IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014.
24. D. Guo and R. Pellizzoni, "A requests bundling DRAM controller for mixed-criticality systems, " in IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2017.
25. L. Ecco and R. Ernst, "Tackling the bus turnaround overhead in real-Time SDRAM controllers, " IEEE Transactions on Computers, 2017.
26. D. Guo, M. Hassan, R. Pellizzoni, and H. Patel, "A comparative study of predictable DRAM controllers, " ACM Transactions on Embedded Computing Systems (TECS), 2018.
27. "Micron RLDRAM3 SDRAM product flyer, " Micron Technology Inc. Accessed: 2018-09-12. [Online]. Available: https://www.micron.com/%7E/media/documents/products/product-flyer/rldram3%5Fproduct%5Fflyer.pdf
28. C. Toal, D. Burns, K. McLaughlin, S. Sezer, and S. O'Kane, "An RLDRAM II implementation of a 10Gbps shared packet buffer for network processing, " in NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2007.
29. S. Phadke and S. Narayanasamy, "MLP aware heterogeneous memory system, " in IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011.
30. N. Chatterjee, M. Shevgoor, R. Balasubramonian, A. Davis, Z. Fang, R. Illikkal, and R. Iyer, "Leveraging heterogeneity in DRAM main memories to accelerate critical word access, " in IEEE/ACM International Symposium on Microarchitecture (MICRO), 2012.
31. R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckmann, T. Mitra et al., "The worstcase execution-Time problem-overview of methods and survey of tools, " ACM Transactions on Embedded Computing Systems (TECS), 2008.
32. M. Hassan, "Variability windows for predictable DDR controllers, a technical report, " https://ece.uwaterloo.ca/%7Em49hassa/publications/RTSS%5F2018%5FTR.pdf, accessed: 2018-09-28.
33. H. Kim, J. Lee, N. B. Lakshminarayana, J. Sim, J. Lim, and T. Pho, "MacSim: A CPU-GPU heterogeneous simulation framework user guide, " Georgia Institute of Technology, 2012.
34. P. Rosenfeld, E. Cooper-Balis, and B. Jacob, "DRAMSim2: A cycle accurate memory system simulator, " IEEE Computer Architecture Letters (CAL), 2011.
35. D. Guo and R. Pellizzoni, "DRAMController: A simulation framework for real-Time DRAM controllers, " 2016, retrievd 2018. [Online]. Available: https://ece.uwaterloo.ca/%7Erpellizz/techreps/dramcontroller.pdf
36. J. A. Poovey, T. M. Conte, M. Levy, and S. Gal-On, "A benchmark characterization of the EEMBC benchmark suite, " IEEE micro, 2009.
37. "Arria 10 FPGA development kit, user guide, " Intel. Accessed: 2018-09-12. [Online]. Available: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug%5Fa10-fpga-prod-devkit.pdf
38. "VCU110 evaluation board, user guide, " xilnix. Accessed: 2018-09-12. [Online]. Available: https://www.xilinx.com/support/documentation/boards%5Fand%5Fkits/vcu110/ug1073-vcu110-eval-bd.pdf
39. "Developing high-speed memory interfaces: The LatticeSCM FPGA advantage, a white paper, " Lattice Semiconductors. Accessed: 2018-09-12. [Online]. Available: http://www.latticesemi.com/view%5Fdocument? document%5Fid=18926
40. "RLDRAM 3 controller core, " Northwest Logic. Accessed: 2018-09-12. [Online]. Available: https://nwlogic.com/products/docs/RLDRAM% 5F3%5FController%5FCore.pdf