메뉴 건너뛰기




Volumn , Issue , 2011, Pages 956-961

MLP aware heterogeneous memory system

Author keywords

[No Author keywords available]

Indexed keywords

CYCLE-ACCURATE SIMULATION; HETEROGENEOUS MEMORY; KEY PARAMETERS; MAIN MEMORY; MEMORY ACCESS; MEMORY MODULES; MEMORY REQUIREMENTS; MEMORY SYSTEMS; MULTI-CORE SYSTEMS; OPERATING SYSTEMS; SYSTEM'S PERFORMANCE; THREE PARAMETERS;

EID: 79957551382     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (61)

References (22)
  • 2
    • 79957555163 scopus 로고    scopus 로고
    • DDR3 SDRAM Part Catalog. http://www.micron.com/partscatalog. html?categoryPath=products/parametric/dram/ddr3-sdram.
    • DDR3 SDRAM Part Catalog
  • 3
  • 6
    • 79957574297 scopus 로고    scopus 로고
    • Reduced latency dram (rldram). http://www.micron.com/products/ ProductDetails.html?product=products/dram/MT49H16M16FM-33.
    • Reduced Latency Dram (Rldram)
  • 7
    • 84870455720 scopus 로고    scopus 로고
    • SPEC CPU2006. http://www.spec.org/cpu2006.
    • SPEC CPU2006
  • 9
    • 76749124429 scopus 로고    scopus 로고
    • Application-aware prioritization mechanisms for on-chip networks
    • R. Das, O. Mutlu, T. Moscibroda, and C. R. Das. Application-aware prioritization mechanisms for on-chip networks. In MICRO, pages 280-291, 2009.
    • (2009) MICRO , pp. 280-291
    • Das, R.1    Mutlu, O.2    Moscibroda, T.3    Das, C.R.4
  • 13
    • 84944403811 scopus 로고    scopus 로고
    • Single-isa heterogeneous multi-core architectures: The potential for processor power reduction
    • R. Kumar, K. I. Farkas, N. P. Jouppi, P. Ranganathan, and D. M. Tullsen. Single-isa heterogeneous multi-core architectures: The potential for processor power reduction. In MICRO, pages 81-92, 2003.
    • (2003) MICRO , pp. 81-92
    • Kumar, R.1    Farkas, K.I.2    Jouppi, N.P.3    Ranganathan, P.4    Tullsen, D.M.5
  • 16
    • 33644903196 scopus 로고    scopus 로고
    • Efficient runahead execution: Power-efficient memory latency tolerance
    • DOI 10.1109/MM.2006.10
    • O. Mutlu, H. Kim, and Y. N. Patt. Efficient runahead execution: Power-efficient memory latency tolerance. IEEE Micro, 26(1):10-20, 2006. (Pubitemid 43380032)
    • (2006) IEEE Micro , vol.26 , Issue.1 , pp. 10-20
    • Mutlu, O.1    Kim, H.2    Patt, Y.N.3
  • 18
    • 70450273507 scopus 로고    scopus 로고
    • Scalable high performance main memory system using phase-change memory technology
    • M. K. Qureshi, V. Srinivasan, and J. A. Rivers. Scalable high performance main memory system using phase-change memory technology. In ISCA, pages 24-33, 2009.
    • (2009) ISCA , pp. 24-33
    • Qureshi, M.K.1    Srinivasan, V.2    Rivers, J.A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.