A comparative study of predictable DRAM controllers

ACM Transactions on Embedded Computing Systems

Volumn 17, Issue 2, 2018, Pages

  Guo, Danlu ^a   Hassan, Mohamed ^a   Pellizzoni, Rodolfo ^a   Patel, Hiren ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

Multicore; Real time; SDRAM controller; WCET

Indexed keywords

CONTROLLERS; EMBEDDED SYSTEMS; RANDOM ACCESS STORAGE; REAL TIME SYSTEMS;

ANALYTICAL PERFORMANCE MODEL; COMMON SIMULATION PLATFORM; DYNAMIC RANDOM ACCESS MEMORY; MULTI CORE; REAL TIME; REAL-TIME EMBEDDED SYSTEMS; SDRAM CONTROLLERS; WCET;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 85042549652     PISSN: 15399087     EISSN: 15583465     Source Type: Journal    
DOI: 10.1145/3158208     Document Type: Article

References (34)

1. Benny Akesson and Kees Goossens. 2011. Memory Controllers for Real-Time Embedded Systems. Springer.
2. Benny Akesson, Kees Goossens, and Markus Ringhofer. 2007. Predator: A predictable SDRAM memory controller. In IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis. 251–256.
3. Roman Bourgade, Clément Ballabriga, Hugues Cassé, Christine Rochange, and Pascal Sainrat. 2008. Accurate analysis of memory latencies for WCET estimation. In International Conference on Real-Time and Network Systems (RTNS’08).
4. Leonardo Ecco and Rolf Ernst. 2015. Improved DRAM timing bounds for real-time DRAM controllers with read/write bundling. In Real-Time Systems Symposium. 53–64.
5. Leonardo Ecco, Adam Kostrzewa, and Rolf Ernst. 2016. Minimizing DRAM rank switching overhead for improved timing bounds and performance. In Euromicro Conference on Real-Time Systems (ECRTS’16).
6. Leonardo Ecco, Sebastian Tobuschat, Selma Saidi, and Rolf Ernst. 2014. A mixed critical memory cntroller using bank privatization and fixed priority scheduling. In Embedded and Real-Time Computing Systems and Applications (RTCSA’14). 1–10.
7. Manil Dev Gomony, Benny Akesson, and Kees Goossens. 2013. Architecture and optimal configuration of a real-time multi-channel memory controller. In Design, Automation & Test in Europe Conference & Exhibition (DATE’13). IEEE, 1307–1312.
8. Sven Goossens, Benny Akesson, and Kees Goossens. 2013. Conservative open-page policy for mxed time-criticality memory cntrollers. In Proceedings of the Conference on Design, Automation and Test in Europe. EDA Consortium, 525–530.
9. Danlu Guo and Rodolfo Pellizzoni. 2016. DRAMController: A simulation framework for real-time DRAM controllers. Retrieved December 2016, from https://ece.uwaterloo.ca/ rpellizz/techreps/dramcontroller.pdf.
10. Mohamed Hassan, Hiren Patel, and Rodolfo Pellizzoni. 2015. A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems. In Real-Time and Embedded Technology and Applications Symposium (RTAS’15). 307–316.
11. Javier Jalle, Eduardo Quiñones, Jaume Abella, Luca Fossati, Marco Zulianello, and Fransisco J. Cazorla. 2014. A dual-criticality memory controller (DCmc): Proposal and evaluation of a space case study. In Real-Time Systems Symposium (RTSS’14). 207–217.
12. DDR3 SDRAM JEDEC. 2008. JEDEC JESD79-3B. 2008.
13. Hokeun Kim, David Broman, Edward A. Lee, Michael Zimmer, Aviral Shrivastava, and Junkwang Oh. 2015. A predictable and command-level priority-based DRAM controller for mixed-criticality systems. In Real-Time and Embedded Technology and Applications Symposium (RTAS’15). 317–326.
14. Hyoseung Kim, Dionisio de Niz, Björn Andersson, Mark Klein, Onur Mutlu, and Ragunathan Rajkumar. 2014. Bounding memory interference delay in COTS-based multi-core systems. In Real-Time and Embedded Technology and Applications Symposium (RTAS’14). IEEE, 145–154.
15. H. Kim, J. Lee, N. Lakshminarayana, J. Lim, and T. Pho. 2012. Macsim: Simulator for heterogeneous architecture.
16. Jung-Eun Kim, Man-Ki Yoon, Richard Bradford, and Lui Sha. 2014. Integrated modular avionics (IMA) partition scheduling with conflit-free I/O for multicore avionics systems. In Computer Software and Applications Conference (COMP-SAC’14). IEEE, 321–331.
17. Yoongu Kim, Dongsu Han, Onur Mutlu, and Mor Harchol-Balter. 2010. ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. In International Symposium on High-Performance Computer Architecture. IEEE, 1–12.
18. Y. Kim, M. Papamichael, O. Mutlu, and M. Harchol-Balter. 2010. Thread cluster memory scheduling: Exploiting differences in memory access behavior. In 43rd Annual IEEE/ACM International Symposium on Microarchitecture. IEEE, 65–76.
19. Yoongu Kim, Weikun Yang, and Onur Mutlu. 2015. Ramulator: A fast and extensible DRAM simulator. CAL (2015).
20. Yogen Krishnapillai, Zheng Pei Wu, and Rodolfo Pellizoni. 2014. ROC: A rank-switching, open-row DRAM controller for time-predictable systems. In Euromicro Conference on Real-Time Systems (ECRTS’14).
21. Yonghui Li, Benny Akesson, and Kees Goossens. 2014. Dynamic command scheduling for real-time memory controllers. In Euromicro Conference on Real-Time Systems (ECRTS’14). 3–14.
22. Yonghui Li, Benny Akesson, Kai Lampka, and Kees Goossens. 2016. Modeling and verification of dynamic command scheduling for real-time memory controllers. In Real-Time and Embedded Technology and Applications Symposium (RTAS’16). 1–12.
23. Isaac Liu, Jan Reineke, and Edward A. Lee. 2010. A PRET architecture supporting concurrent programs with composable timing properties. In Conference Record of the 44th Asilomar Conference on Signals, Systems and Computers. 2111–2115.
24. Onur Mutlu and Thomas Moscibroda. 2008. Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems. In ACM SIGARCH Computer Architecture News, Vol. 36. IEEE Computer Society, 63–74.
25. Marco Paolieri, Eduardo Quiñones, Fransisco J. Cazorla, and Mateo Valero. 2009. An analyzable memory controller for hard real-time CMPs. Embedded System Letters (ESL) 1 (2009), 86–90.
26. Jason Poovey. 2007. Characterization of the EEMBC benchmark suite. North Carolina State University.
27. Jan Reineke, Isaac Liu, Hiren D. Patel, Sungjun Kim, and Edward A. Lee. 2011. PRET DRAM controller: Bank privatization for predictability and temporal isolation. In IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. 99–108.
28. Paul Rosenfeld, Elliott Cooper-Balis, and Bruce Jacob. 2011. DRAMSim2: A cycle accurate memory system simulator. IEEE Computer Architecture Letters 10, 1 (2011), 16–19.
29. L. Subramanian, D. Lee, V. Seshadri, H. Rastogi, and O. Mutlu. 2016. BLISS: Balancing performance, fairness and complexity in memory access schedyuling. IEEE Transactions on Parallel and Distributed Systems 27 (2016), 3071–3087.
30. Prathap Kumar Valsan and Heechul Yun. 2015. MEDUSA: A predictable and high-performance DRAM controller for multicore based embedded systems. In Cyber-Physical Systems, Networks, and Applications (CPSNA’15). 86–93.
31. Reinhard Wilhelm, Daniel Grund, Jan Reineke, Marc Schlickling, Markus Pister, and Christian Ferdinand. 2009. Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28 (2009), 966.
32. Zheng Pei Wu. 2013. Worst Case Analysis of DRAM Latency in Hard Real Time Systems. Master’s thesis. University of Waterloo.
33. Zheng Pei Wu, Yogen Krish, and Rodolfo Pellizzoni. 2013. Worst case analysis of DRAM latency in multi-requestor systems. In Real-Time Systems Symposium (RTSS’13). 372–383.
34. Heechul Yun, Rodolfo Pellizzon, and Prathap Kumar Valsan. 2015. Parallelism-aware memory interference delay analysis for COTS multicore systems. In Euromicro Conference on Real-Time Systems (ECRTS’15). 184–195.