Improved DRAM Timing Bounds for Real-Time DRAM Controllers with Read/Write Bundling

Proceedings - Real-Time Systems Symposium

Volumn 2016-January, Issue , 2016, Pages 53-64

  Ecco, Leonardo ^a   Ernst, Rolf ^a  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

DRAM; DRAM analysis; DRAM command bundling; DRAM command overhead; DRAM optimized schedling; DRAM scheduling; DRAM timing bounds; read write overhead; read write bundling; real time

Indexed keywords

CONTROLLERS; DYNAMIC RANDOM ACCESS STORAGE; INTERACTIVE COMPUTER SYSTEMS; SYSTEM BUSES; TIMING CIRCUITS;

DATA BUS; MEMORY CONTROLLER; READ WRITE OVERHEAD; READ/WRITE BUNDLING; REAL TIME; STATE OF THE ART; TIMING ANALYSIS;

REAL TIME SYSTEMS;

EID: 84964658604     PISSN: 10528725     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTSS.2015.13     Document Type: Conference Paper

References (17)

1. B. Akesson, K. Goossens, and M. Ringhofer, "Predator: A Predictable SDRAM Memory Controller," in Int'l Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). ACM Press New York, NY, USA, Sep. 2007, pp. 251-256.
2. J. Reineke, I. Liu, H. D. Patel, S. Kim, and E. A. Lee, "Pret dram controller: bank privatization for predictability and temporal isolation," in Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, ser. CODES+ISSS '11. New York, NY, USA: ACM, 2011, pp. 99-108.
3. M. Paolieri, E. Quiones, F. Cazorla, and M. Valero, "An analyzable memory controller for hard real-time cmps," Embedded Systems Letters, IEEE, vol. 1, no. 4, pp. 86-90, Dec 2009.
4. J. Jalle, E. Quinones, J. Abella, L. Fossati, M. Zulianello, and F. Cazorla, "A dual-criticality memory controller (dcmc): Proposal and evaluation of a space case study," in Real-Time Systems Symposium (RTSS), 2014 IEEE, Dec 2014, pp. 207-217.
5. Z. P. Wu, Y. Krish, and R. Pellizzoni, "Worst case analysis of dram latency in multi-requestor systems," in Real-Time Systems Symposium (RTSS), 2013 IEEE 34th, Dec 2013, pp. 372-383.
6. Y. Krishnapillai, Z. P. Wu, and R. Pellizzoni, "A rank-switching, openrow dram controller for time-predictable systems," in Real-Time Systems (ECRTS), 2014 26th Euromicro Conference on, July 2014, pp. 27-38.
7. H. Yun, R. Mancuso, Z.-P. Wu, and R. Pellizzoni, "Palloc: Dram bankaware memory allocator for performance isolation on multicore platforms," in IEEE Real-Time and Embedded Technology and Applications Symposium, vol. 356, 2014.
8. L. Liu, Z. Cui, M. Xing, Y. Bao, M. Chen, and C. Wu, "A software memory partition approach for eliminating bank-level interference in multicore systems," in Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques, ser. PACT '12. New York, NY, USA: ACM, 2012, pp. 367-376.
9. N. Suzuki, H. Kim, D. d. Niz, B. Andersson, L. Wrage, M. Klein, and R. Rajkumar, "Coordinated bank and cache coloring for temporal protection of memory accesses," in Computational Science and Engineering (CSE), 2013 IEEE 16th International Conference on. IEEE, 2013, pp. 685-692.
10. H. Kim, D. de Niz, B. Andersson, M. Klein, O. Mutlu, and R. Rajkumar, "Bounding memory interference delay in cots-based multi-core systems," in Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014 IEEE 20th, April 2014, pp. 145-154.
11. JESD79-2F: DDR2 SDRAM Specification, JEDEC, Arlington, Va, USA, Nov. 2009.
12. JESD79-3F: DDR3 SDRAM Specification, JEDEC, Arlington, Va, USA, Jul. 2012.
13. M. Paolieri, E. Quiñones, and F. J. Cazorla, "Timing effects of ddr memory systems in hard real-time multicore architectures: Issues and solutions," ACM Trans. Embed. Comput. Syst., vol. 12, no. 1s, pp. 64:1-64:26, Mar. 2013.
14. R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand, "Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, no. 7, pp. 966-978, July 2009.
15. R. Bourgade, C. Ballabriga, H. Cassé, C. Rochange, and P. Sainrat, "Accurate analysis of memory latencies for wcet estimation," in 16th International Conference on Real-Time and Network Systems (RTNS 2008), 2008.
16. B. Bhat and F. Mueller, "Making dram refresh predictable," Real-Time Systems, vol. 47, no. 5, pp. 430-453, 2011.
17. M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, and R. Brown, "Mibench: A free, commercially representative embedded benchmark suite," in Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop on, Dec 2001, pp. 3-14.