Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator

Proceedings of the IEEE VLSI Test Symposium

Volumn 2018-April, Issue , 2018, Pages 1-6

  Zhang, Jeff ^a   Gu, Tianyu ^a   Basu, Kanad ^a   Garg, Siddharth ^a  

^a POLYTECHNIC UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEEP NEURAL NETWORKS; DROPS; VLSI CIRCUITS;

CLASSIFICATION ACCURACY; COMPUTATIONAL COSTS; HARDWARE ACCELERATION; MATRIX MULTIPLICATION; NOVEL STRATEGIES; PERMANENT FAULTS; PROCESSING UNITS; RUN-TIME PERFORMANCE;

SYSTOLIC ARRAYS;

EID: 85048375978     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2018.8368656     Document Type: Conference Paper

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