2.488 Gb/s Si-Bipolar clock and data recovery IC with robust loss of signal detection

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 40, Issue , 1997, Pages 246-247

  Walker, R ^a   Stout, C ^a   Yen, C S ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; BIT ERROR RATE; BROADBAND AMPLIFIERS; FREQUENCY RESPONSE; INTEGRATED CIRCUIT LAYOUT; PHASE LOCKED LOOPS; SIGNAL DETECTION; VARIABLE FREQUENCY OSCILLATORS;

CLOCK AND DATA RECOVERY CIRCUITS (CDR); LOSS OF SIGNAL (LOS) DETECTOR;

TIMING CIRCUITS;

EID: 0031074346     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)