622Mb/s CMOS clock recovery PLL with time-interleaved phase detector array

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 198-199

  Lee, Inyeo ^a   Yoo, Changsik ^a   Kim, Wonchan ^a   Chai, Sanghoon ^a   Song, Wonchul ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CLOCKS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DATA COMMUNICATION SYSTEMS; DELAY CIRCUITS; DETECTOR CIRCUITS; EMITTER COUPLED LOGIC CIRCUITS; LOGIC GATES; SIGNAL DETECTION; TIMING CIRCUITS; VARIABLE FREQUENCY OSCILLATORS;

CHARGE PUMP; CHIP MICROGRAPH; CLOCK RECOVERY CIRCUITS; CURRENT MODE LOGIC; JITTER; TIME INTERLEAVED PHASE DETECTOR ARRAY;

PHASE LOCKED LOOPS;

EID: 0030081924     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)