3DSDM: A 3 data-source diagnostic method

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2003-January, Issue , 2003, Pages 117-123

  Hariri, Y ^a   Thibeault, C ^a  

^a ÉCOLE DE TECHNOLOGIE SUPÉRIEURE   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DEFECTS; DESIGN FOR TESTABILITY; FAULT TOLERANCE; LARGE SCALE SYSTEMS;

BRIDGING FAULT; CIRCUIT UNDER TEST; DATA-SOURCES; DIAGNOSIS METHODS; HYBRID METHOD; LOGICAL BEHAVIOR; PARASITIC CAPACITANCE; POTENTIAL FAULTS;

FAULT DETECTION;

EID: 84971265454     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TSM.2005.1250102     Document Type: Conference Paper

References (25)

1. IEEE Test Technology Technical Committee, "A D&T Roundtable: Deep-Submicron Test", IEEE Design and Test of Computers, vol. 13, no. 3, pp. 102-108, Fall 1996
2. IEEE Test Technology Technical Committee, "Sematech Experiment Roundtable", IEEE Design and Test of Computers, vol. 15, no. 1, p. 89, Jan-Mar. 1998
3. D. P. Vallett, "IC Failure Analysis: The Importance of Test and Diagnostics", IEEE Design and Test of Computers, vol. 13, no. 3, pp. 76-82, July-Sept. 1998.
4. S. Chakravarty and M. Liu, "Algorithm for IDDQ Measurement Based Diagnosis of Bridging Faults", J. Electronic Testing: Theory and Applications, vol. 3, no 4, pp. 377-386, Dec. 1992
5. H. Tkahashi, N. Yanagida, and Y. Takamatsu, "Enhancing Multiple Fault Diagnosis in Combinatorial Circuits Based on Sensitized Paths and EB Testing", IEEE Fourth Asian Test Conf., pp. 58-64, 1995.
6. P. Night, D. Vallett, J. Wright, F. Motika, D. Forlenza, R. Kurtulik, and W. Chong, "Failure Analysis of Timing and Iddq-Only Failures from the SEMATECH Test Method Experiment". IEEE Int'l Test Conf., pp. 43-52, 1998.
7. R. C. Aitken, "Diagnosis of Leakage Faults with IDDQ", J. Electronic Testing: Theory and Application, vol. 3, no. 4, pp. 367-376, Dec. 1992.
8. C. Thibeault, "A Novel Probabilistic Approach for IC Diagnosis Based on Differential Quiescent Current Signatures", IEEE VLSI Test Symp., pp. 80-85, 1997.
9. J. A. Waicukauski and E. Lindbloom, "Failure Diagnosis of Structured VLSI", IEEE Design and Test of Computers, vol. 6, no. 4, pp. 49-60, Fall 1989.
10. P. Nigh, D. Forlenza, and F. Motika", Application and Analysis of Iddq Diagnostic Software", IEEE Int'l Test Conf., pp. 319-327, 1997.
11. E. Isern and J. Figueras, "IDDQ Test and Diagnosis of CMOS Circuits", IEEE Design and Test of Computers, vol. 12, no. 4, pp. 60-67, Winter 1995.
12. J. Saxena et al., "On Applying Non-Classical Defect Models to Automated Diagnosis", IEEE Int'l Test Conf., pp. 748-757, 1998.
13. H. Takahashi, N. Yanagida, and Y. Takamatsu, "Enhancing Multiple Fault Diagnosis in Combinatorial Circuits Based on Sensitized Paths and EB Testing", IEEE Fourth Asian Test Conf., pp. 58-64, 1995.
14. R. C. Aitken, "Fault Location with Current Monitoring", Int'l Test Conf., pp. 623-635, 1991.
15. M. Abramovici, M. Breuer, and A. Friedman, "Digital System Testing and Testable Design", IEEE Press, Piscataway, NJ, 1990.
16. J. M. Soden, C. F Hawkins, and A. C Miller, "Identifying Defects in Deep-Submicron CMOS ICs", IEEE Spectrum, vol. 33, no. 9, pp. 66-71 Sept. 1996
17. A. E Gattiker and W. Maly, "Current Signatures", IEEE VLSI Test Symp., pp 112-117, s1996.
18. P. Maxwell, R. Aitken, and L. Huismann, "The Effect on Quality of Non-Uniform fault Coverage and Fault Probability", IEEE Int'l Test Conf., pp. 739-746, 1994.
19. C. Stroud, J. Emmert. J. Bailey, K. Chhor, D. Nikolic", Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development", Int. Test Conf., 2000, pp 760-769.
20. Z. Stanojevic, D. Walker, "Fed Ex TM - A Fast Bridging Fault Extractor", IEEE Int'l Test Conf., pp. 696-704, 2001.
21. R. Y. Li, S. C. Diehl, and S. Harrison", Power Supply Noise Testing of VLSI chips", Int'l Test Conf., 1983, pp. 366-369.
22. C. F. Hawkins and J. Soden, "Electrical Characteristics and Testing for Gate Oxide Shorts in CMOS ICs", Int'l Test Conf., 1985, pp. 544-555.
23. J. Shen, W. Maly, and F. Ferguson, "Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells", Int'l Test Conf., 1984, pp. 390-399.
24. C. Thibeault", Diagnosis Method Based on Iddq Probabilistic Signatures: Theory and Results", Journal of Electronic Testing, Kluwer, vol. 16, no 4, 2000, p. 339-353.
25. C. Thibeault", On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults", IEEE Trans. On Computers, vol. 49, no 6, June 2000, p. 575-587.