Transition pattern coding: An approach to reduce energy in interconnect

European Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 348-351

  Sotiriadis, Paul P ^a   Wang, Alice ^a   Chandrakasan, Anantha ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITIVE COUPLINGS; COMPREHENSIVE ENERGY; DISSIPATION MODELS; PARASITIC CAPACITANCE; SUBMICRON TECHNOLOGIES; SWITCHING ENERGY; TRANSITION PATTERNS; TRANSITION PROFILES;

WIRE;

ENERGY DISSIPATION;

EID: 34548834356     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. M. Stan, W. Burleson, "Low-power encodings for global communication in cmos VLSI," IEEE Transactions on VLSI Systems, pp. 49-58, Vol. 5, No. 4, Dec. 1997.
2. S. Ramprasad, N. Shanbhag, I. Hajj, "A coding framework for low-power address and data busses," IEEE Transactions on VLSI Systems, pp. 212-221, Vol. 7, No. 2, June 1999.
3. J.M. Rabaey, Digital Integrated circuits. Prentice Hall 1996.
4. H.B. Bakoglou, Circuits, Interconnections, and Packaging in VLSI. Addison-Wesley Pub. Co., c1990