Fast, minimal decoding complexity, systematic (13, 8) single-error-correcting codes for on-chip DRAM applications

Electronics Letters

Volumn 37, Issue 7, 2001, Pages 438-440

  Kazeminejad A ^a  

^a UNIVERSITÉ PARIS SACLAY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; DECODING; ERROR CORRECTION; MICROPROCESSOR CHIPS; SHIFT REGISTERS;

LINEAR FEEDBACK SHIFT REGISTERS (LFSR); REED-SOLOMON CODES; SINGLE-ERROR-CORRECTING CODES;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0035967021     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20010316     Document Type: Article

References (4)

1. Design of a fault-tolerant three-dimensional dynamic random-access memory with on-chip error-correcting circuit
2. Random double-bit error correcting generalised array codes
3. A systematic (12, 8) code for correcting single errors and detecting adjacent errors
4. A note on a systematic (12, 8) code for correcting single errors and detecting adjacent errors