Power supply noise aware floorplanning and decoupling capacitance placement

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 489-495

  Zhao, Shiyou ^a   Roy, K ^a   Koh, Cheng Kok ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; CAPACITANCE; CAPACITANCE MEASUREMENT; COMPUTER AIDED DESIGN; COST FUNCTIONS; DESIGN; EMBEDDED SYSTEMS; RECONFIGURABLE HARDWARE; VLSI CIRCUITS; WIRE;

BENCHMARK CIRCUIT; CIRCUIT MODULES; DE-COUPLING CAPACITANCE; FLOOR-PLANNING; POWER-SUPPLY NOISE; SPATIAL CORRELATIONS; SWITCHING ACTIVITIES; WIRE LENGTH;

INTEGRATED CIRCUIT TESTING;

EID: 84962229184     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994968     Document Type: Conference Paper

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