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Volumn , Issue , 2001, Pages 377-380

Deep-submicron CMOS process integration of HfO2 gate dielectric with poly-si gate

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATE DIELECTRICS; HAFNIUM OXIDES; POLYCRYSTALLINE MATERIALS; SEMICONDUCTOR DEVICES;

EID: 84961795092     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISDRS.2001.984521     Document Type: Conference Paper
Times cited : (7)

References (7)
  • 2
    • 0031275325 scopus 로고    scopus 로고
    • Predicting CMOS speed with gate oxide voltage scaling and interconnect loading effects
    • et al, Nov.
    • K. Chen, C. Hu, P. Fang, M. R. Lin and D. L. Wollensen, "Predicting CMOS speed with gate oxide voltage scaling and interconnect loading effects", et al, IEEE Tran. Electron Devices, vol. 44, pp.1951-57, Nov. 1997
    • (1997) IEEE Tran. Electron Devices , vol.44 , pp. 1951-1957
    • Chen, K.1    Hu, C.2    Fang, P.3    Lin, M.R.4    Wollensen, D.L.5
  • 3
    • 0033281224 scopus 로고    scopus 로고
    • Quantum effect in oxide thickness determination from capacitance measurement
    • June
    • K. J. Yang, Y.-C. King and C. Hu, "Quantum effect in oxide thickness determination from capacitance measurement", in Proc. Symp. VLSI Tech., June 1999, pp.77-78.
    • (1999) Proc. Symp. VLSI Tech. , pp. 77-78
    • Yang, K.J.1    King, Y.-C.2    Hu, C.3
  • 4
    • 0033725602 scopus 로고    scopus 로고
    • Modeling gate and substrate currents due to conduction and valance band electron and hole tunneling
    • June
    • W.-C. Lee and C. Hu, "Modeling gate and substrate currents due to conduction and valance band electron and hole tunneling", in Proc. Symp. VLSI Tech., June 2000, pp.198-199.
    • (2000) Proc. Symp. VLSI Tech. , pp. 198-199
    • Lee, W.-C.1    Hu, C.2
  • 5
    • 0034318446 scopus 로고    scopus 로고
    • Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric
    • Nov.
    • Y.-C. Yeo, Q. Lu, W.-C. Lee, T.-J. King; C. Hu, X. Wang, X. Guo, T. P. Ma, "Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric", in IEEE Electron Device Letters, vol.21, no.11, pp.540-542, Nov. 2000.
    • (2000) IEEE Electron Device Letters , vol.21 , Issue.11 , pp. 540-542
    • Yeo, Y.-C.1    Lu, Q.2    Lee, W.-C.3    King, T.-J.4    Hu, C.5    Wang, X.6    Guo, X.7    Ma, T.P.8
  • 6
    • 0034446314 scopus 로고    scopus 로고
    • Very high performance 40 nm CMOS with ultra-thin nitride/oxynitride stack gate dielectric and pre-deoped dual poly-Si gate electrodes
    • Dec.
    • X. Qi, J. Jeon, P. Sachdey, B. Yu, K. C. Saraswat and M.-R. Lin, "Very high performance 40 nm CMOS with ultra-thin nitride/oxynitride stack gate dielectric and pre-deoped dual poly-Si gate electrodes", IEDM Tech. Dig., Dec. 2000, pp.860-862.
    • (2000) IEDM Tech. Dig. , pp. 860-862
    • Qi, X.1    Jeon, J.2    Sachdey, P.3    Yu, B.4    Saraswat, K.C.5    Lin, M.-R.6
  • 7
    • 0034187380 scopus 로고    scopus 로고
    • Band offsets of wide-band-gap oxides and implications for future electronic devices
    • J. Robertson, "Band offsets of wide-band-gap oxides and implications for future electronic devices", J. Vac. Sci. Tech., B18(3), pp. 1785-1791, 2000.
    • (2000) J. Vac. Sci. Tech. , vol.B18 , Issue.3 , pp. 1785-1791
    • Robertson, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.