Boolean satisfiability with transitivity constraints

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1855, Issue , 2000, Pages 85-98

  Bryant, Randal E ^a   Velev, Miroslav N ^b  

^a Carnegie Mellon University   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY DECISION DIAGRAMS; COMPUTER AIDED ANALYSIS;

BOOLEAN SATISFIABILITY; BOOLEAN SATISFIABILITY PROBLEMS; LOGIC OF EQUALITIES; ORDERED BINARY DECISION DIAGRAMS; PROPOSITIONAL VARIABLES; SATISFIABILITY PROBLEMS; SATISFYING ASSIGNMENTS; UNINTERPRETED FUNCTIONS;

FORMAL LOGIC;

EID: 84944393003     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/10722167_10     Document Type: Conference Paper

References (14)

1. R. E. Bryant, “Graph-based algorithms for Boolean function manipulation”, IEEE Transactions on Computers, Vol. C-35, No. 8 (August, 1986), pp. 677–691.
2. R. E. Bryant, S. German, and M. N. Velev, “Exploiting positive equality in a logic of equality with uninterpreted functions,” Computer-Aided Verification (CAV’99), N. Halbwachs, and D. Peled eds., LNCS 1633, Springer-Verlag, July, 1999, pp. 470–482.
3. R. E. Bryant, S. German, and M. N. Velev, “Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic,” Technical report CMU-CS-99-115, Carnegie Mellon University, 1999. Available as: http://www.cs.cmu.edu/~bryant/pubdir/cmu-cs-99-115.ps.
4. R. E. Bryant, and M. N. Velev, “Boolean satisfiability with transitivity constraints,” Technical report CMU-CS-00-101, Carnegie Mellon University, 2000. Available as: http://www.cs.cmu.edu/~bryant/pubdir/cmu-cs-00-101.ps.
5. [BD94] J. R. Burch, and D. L. Dill, “Automated verification of pipelined microprocessor control,” Computer-Aided Verification (CAV’94), D. L. Dill, ed., LNCS 818, Springer-Verlag, June, 1994, pp. 68–80.
6. J. R. Burch, “Techniques for verifying superscalar microprocessors,” 33rd Design Automation Conference (DAC’96), June, 1996, pp. 552–557.
7. [GSZAS98] A. Goel, K. Sajid, H. Zhou, A. Aziz, and V. Singhal, “BDD based procedures for a theory of equality with uninterpreted functions,” Computer-Aided Verification (CAV’98), A. J. Hu and M. Y. Vardi, eds., LNCS 1427, Springer-Verlag, June, 1998, pp. 244–255.
8. [HP96] J. L. Hennessy, and D. A. Patterson, Computer Architecture: A Quantitative Approach, 2nd edition Morgan-Kaufmann, San Francisco, 1996.
9. F. T. Leighton, Introduction to Parallel Algorithms and Architectures: Arrays, Trees, and Hypercubes, Morgan Kaufmann, 1992.
10. [MS99] J. P. Marques-Silva, and K. A. Sakallah, “Grasp: A search algorithm for propositional satisfiability,” IEEE Transactions on Computers, Vol. 48, No. 5 (May, 1999), pp. 506–521.
11. [M99] J. P. Marques-Silva, “The impact of branching heuristics in propositional satisfiability algorithms,” 9th Portugese Conference on Artificial Intelligence, September, 1999.
12. D. Rose, “Triangulated graphs and the elimination process,” Journal of Mathematical Analysis and Applications, Vol. 32 (1970), pp. 597–609.
13. [VB99] M. N. Velev, and R. E. Bryant, “Superscalar processor verification using efficient reductions of the logic of equality with uninterpreted functions,” Correct Hardware Design and Verification Methods (CHARME’99), L. Pierre, and T. Kropf, eds., LNCS 1703, Springer-Verlag, September, 1999, pp. 37–53.
14. M. Yannakakis, “Computing the minimum fill-in is NP-complete,” SIAM Journal of Algebraic and Discrete Mathematics, Vol. 2 (1981), pp. 77–79.