Left edge algorithm and the tree growing technique in block-test scheduling under power constraints

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2000, Pages 417-422

  Muresan, Valentin ^a   Wang, Xiaojun ^a   Muresan, Valentina ^a   Vladutiu, Mircea ^a  

^a DUBLIN CITY UNIVERSITY   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CONSTRAINT THEORY; ELECTRIC POWER SUPPLIES TO APPARATUS; SCHEDULING; VLSI CIRCUITS;

BLOCK TEST SCHEDULING; LEFT EDGE ALGORITHM; TREE GROWING TECHNIQUE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033743219     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vtest.2000.843873     Document Type: Article

References (6)