Using PARBIT to implement partial run-time reconfigurable systems

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2438 LNCS, Issue , 2002, Pages 182-191

  Horta, Edson L ^a   Lockwood, John W ^b   Kofuji, Sérgio T ^a  

^a UNIVERSITY OF SÃO PAULO   (Brazil)

^b WASHINGTON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY SEQUENCES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE ARCHITECTURES; STRUCTURAL DESIGN;

APPLICATION EXAMPLES; BIT STREAM; BITSTREAMS; FPGA CONFIGURATION; FPGA DEVICES; RECONFIGURABLE; RUN-TIME RECONFIGURABLE; RUN-TIME RECONFIGURABLE SYSTEMS;

RECONFIGURABLE HARDWARE;

EID: 79955142108     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-46117-5_20     Document Type: Conference Paper

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