Partially reconfigurable cores for Xilinx Virtex

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2438 LNCS, Issue , 2002, Pages 292-301

  Dyer, Matthias ^a   Plessl, Christian ^a   Platzner, Marco ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

AUDIO STREAMING; COMPUTATION THEORY; COPROCESSOR; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT DESIGN; PROGRAM PROCESSORS; RECONFIGURABLE ARCHITECTURES; SYSTEM-ON-CHIP;

CONFIGURABLE SYSTEMS; FEED THROUGH; FULLY OPERATIONAL; HIGH-LEVEL DESIGN; PARTIAL CONFIGURATION; PARTIAL RECONFIGURATION; RECONFIGURABLE; RECONFIGURABLE COPROCESSORS;

RECONFIGURABLE HARDWARE;

EID: 79955155845     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-46117-5_31     Document Type: Conference Paper

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