System level exploration of a STT-MRAM based level 1 data-cache

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 2015-April, Issue , 2015, Pages 1311-1316

  Komalan, Manu Perumkunnil ^a   Tenllado, Christian ^a   Perez, Jose Ignacio Gomez ^a   Fernandez, Francisco Tirado ^a   Catthoor, Francky ^b,c  

^a UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COSINE TRANSFORMS; INTEGRATED CIRCUIT DESIGN; MAGNETIC RECORDING; MRAM DEVICES; RRAM; STATIC RANDOM ACCESS STORAGE;

ARCHITECTURAL MODIFICATION; DYNAMIC POWER CONSUMPTION; GENERAL-PURPOSE SYSTEMS; NON-VOLATILE MEMORY TECHNOLOGY; PERFORMANCE PENALTIES; PERFORMANCE REQUIREMENTS; RESISTIVE RAMS (RERAM); SYSTEM-LEVEL EXPLORATION;

CACHE MEMORY;

EID: 84945895902     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/date.2015.0551     Document Type: Conference Paper

References (13)

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