Feasibility exploration of NVM based I-cache through MSHR enhancements

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2014, Pages

  Komalan, Manu ^a,b   Pérez, José Ignacio Gómez ^a   Tenllado, Christian ^a   Raghavan, Praveen ^b   Hartmann, Matthias ^b   Catthoor, Francky ^b  

^a UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^b IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ARM PROCESSORS; DATA STORAGE EQUIPMENT; MRAM DEVICES; NONVOLATILE STORAGE; VOLTAGE SCALING;

DYNAMIC VOLTAGE SCALING; INSTRUCTION CACHES; LOW SUPPLY VOLTAGES; NON-VOLATILE MEMORY TECHNOLOGY; PERFORMANCE PENALTIES; SPIN TORQUE TRANSFER; SUB-THRESHOLD LEAKAGE; TECHNOLOGY SCALING;

STATIC RANDOM ACCESS STORAGE;

EID: 84903836180     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/DATE2014.034     Document Type: Conference Paper

References (13)

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