Using magnetic ram to build low-power and soft error-resilient l1 cache

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 20, Issue 1, 2012, Pages 19-28

  Sun, Hongbin ^a   Liu, Chuanyin ^a   Xu, Wei ^b   Zhao, Jizhong ^a   Zheng, Nanning ^a   Zhang, Tong ^c  

^a XI'AN JIAOTONG UNIVERSITY   (China)

^b MARVELL SEMICONDUCTOR INC   (United States)

^c RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

Cache; Low power; Magnetic RAM (MRAM); Reliability; Soft error

Indexed keywords

ARCHITECTURAL VULNERABILITY FACTOR; ARCHITECTURE DESIGNS; CACHE; CACHE ARCHITECTURE; DATA CACHES; DESIGN APPROACHES; DYNAMIC ENERGY; ERROR-RESILIENT; FAST READ; HIGH DYNAMIC; LOW LEAKAGE POWER; LOW POWER; MAGNETIC RAMS; MAGNETIC RANDOM ACCESS MEMORIES; MEMORY TECHNOLOGY; NONVOLATILITY; ON-CHIP CACHE; PERFORMANCE DEGRADATION; RADIATION-INDUCED; SOFT ERROR; SRAM BUFFERS; WRITE OPERATIONS;

DEGRADATION; ENERGY EFFICIENCY; ERROR CORRECTION; MAGNETIC LEAKAGE; MAGNETIC STORAGE; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; MRAM DEVICES; RELIABILITY; STATIC RANDOM ACCESS STORAGE;

CACHE MEMORY;

EID: 83655201599     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2090914     Document Type: Article

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