Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2014, Pages

  Noguchi, Hiroki ^a   Ikegami, Kazutaka ^a   Shimomura, Naoharu ^a   Tetsufumi, Tanamoto ^a   Ito, Junichi ^a   Fujita, Shinobu ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

VLSI CIRCUITS;

EMBEDDED DRAM; ERROR CORRECTING CODE; LASTLEVEL CACHES (LLC); LOW POWER; NON-VOLATILE; READ-OUT CIRCUIT; STT-MRAM; TOTAL POWER CONSUMPTION;

CACHE MEMORY;

EID: 84905649965     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2014.6858403     Document Type: Conference Paper

References (5)

1. M. T. Chang et al., 19th HPCA, pp.143-154, 2013.
2. E. Kitagawa et al., IEDM Tech. Dig., pp.677-680, 2012.
3. H. Noguchi, et al., Symp. on VLSI Circuits, pp.108-109, 2013.
4. K. C. Chun, et al., IEEE JSSC, vol.46, no.6, pp.1495-1505, 2011.
5. C. W. Smullen, et al., 17th HPCA, pp.50-61, 2011.