Phase-change memory: Feasibility of reliable multilevel-cell storage and retention at elevated temperatures

IEEE International Reliability Physics Symposium Proceedings

Volumn 2015-May, Issue , 2015, Pages 5B61-5B66

  Stanisavljevic, Milos ^a   Athmanathan, Aravinthan ^a   Papandreou, Nikolaos ^a   Pozidis, Haralampos ^a   Eleftheriou, Evangelos ^a  

^a IBM RESEARCH ZURICH   (Switzerland)

Author keywords

drift; endurance; multilevel cell (MLC) storage; non volatile memories (NVM); Phase change memory (PCM); readout metric

Indexed keywords

DURABILITY; RELIABILITY;

DRIFT; MULTI LEVEL CELL (MLC); NON-VOLATILE MEMORY; PHASE CHANGE MEMORY (PCM); READOUT METRIC;

PHASE CHANGE MEMORY;

EID: 84942853564     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2015.7112747     Document Type: Conference Paper

References (14)

1. Y. Choi, et al., "A 20nm 1. 8V 8Gb PRAM with 40MB/s program bandwidth, " in Proc. Intl. ISSCC Tech. Dig., 2012, pp. 46-48.
2. H. S. Wong, S. Raoux, S. Kim, J. Liang, J. / P. Reifenberg, B. Rajendran, M. Asheghi and K. E. Goodson, "Phase change memory, " Proc. IEEE, vol. 98, no. 12, pp. 2201-2227, 2010.
3. D. Ielmini, D. Sharma, S. Lavizzari, and A. L. Lacaita, "Reliability impact of chalcogenide-structure relaxation in phase-change memory (PCM) cells Part I: Experimental study, " IEEE Trans. Electron Devices, vol. 56, no. 5, pp. 1070-1077, 2009.
4. D. Fugazza, D. Ielmini, S. Lavizzari, and A. L. Lacaita, "Experimental investigation of transport properties in chalcogenide materials through 1/f noise measurements, " Appl. Phys. Lett., vol. 88, pp. 263506, 2006.
5. S. Lavizzari, D. Ielmini, D. Sharma, and A. L. Lacaita, "Reliability impact of chalcogenide-structure relaxation in phase-change memory (PCM) cells-Part II: Physics-based modeling, " IEEE Trans. Electron Devices, vol. 56, no. 5, pp. 1078-1085, May 2009.
6. A. Sebastian, N. Papandreou, A. Pantazi, H. Pozidis and E. Eleftheriou, "Non-resistance-based cell-state metric for phase change memory", Journal of Applied Physics, vol. 110, pp. 084505, Oct. 2011.
7. N. Papandreou, A. Sebastian, A. Pantazi, M. Breitwisch, C. Lam, H. Pozidis, and E. Eleftheriou, "Drift-resilient cell-state metric for multilevel phase-change memory, " in Proc. IEDM Tech. Dig., 2011, pp. 55-58.
8. G. F. Close, U. Frey, M. Breitwisch, H. L. Lung, C. Lam, C. Hagleitner, and E. Eleftheriou, "Device, circuit and system-level analysis of noise in multi-bit phase-change memory, " in Proc. IEDM Tech. Dig., 2010, pp. 660-663.
9. N. Papandreou, T. Antonakopoulos, U. Egger, A. Palli, H. Pozidis, and E. Eleftheriou, "A versatile platform for characterization of solid-state memory channels, " in Proc. DSP, 2013, pp. 1-5.
10. T. Nirschl, J. Philipp, T. Happ, G. Burr, B. Rajendran, M.-H. Lee, A. Schrott, M. Yang, M. Breitwisch, C. Chen, E. Joseph, M. Lamorey, R. Cheek, S.-H. Chen, S. Zaidi, S. Raoux, Y. Chen, Y. Zhu, R. Bergmann, H. L. Lung, and C. Lam, "Write strategies for 2 and 4-bit multi-level phase-change memory, " in Proc. IEDM, 2007, pp. 461-464.
11. N. Papandreou, H. Pozidis, A. Pantazi, A. Sebastian, M. Breitwisch, C. Lam, and E. Eleftheriou, "Programming algorithms for multilevel phasechange memory, " in Proc. ISCAS, 2011, pp. 329-332.
12. N. Papandreou, H. Pozidis, T. Mittelholzer, G. F. Close, M. Breitwisch, C. Lam, and E. Eleftheriou, "Drift-tolerant multilevel phase-change memory, " in Proc. Intl. Memory Workshop (IMW), 2011, pp. 147-150.
13. H. Pozidis, N. Papandreou, A. Sebastian, T. Mittelholzer, M. BrightSky, C. Lam, and E. Eleftheriou, "Reliable MLC Data Storage and Retention in Phase-Change Memory After Endurance Cycling, " in Proc. Intl. Memory Workshop (IMW), May 2013, pp. 100-103.
14. H. Pozidis, T. Mittelholzer, N. Papandreou T. Parnell, and M. Stanisavljevic, "Phase Change Memory Reliability: A Signal Processing and Coding Perspective, " in Proc. TMRC Tech. Dig., Aug. 2014, pp. 81-82.