SPaRe: Selective partial replication for concurrent fault detection in FSMs

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 167-173

  Drineas, Petros ^a   Makris, Yiorgos ^a  

^a Yale University   (United States)

Author keywords

Circuit faults; Circuit testing; Costs; Degradation; Delay; Electrical fault detection; Encoding; Fault detection; Hardware; Logic circuits

Indexed keywords

COMPUTER HARDWARE; COSTS; DEGRADATION; DELAY CIRCUITS; DESIGN; ELECTRIC FAULT LOCATION; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; ENCODING (SYMBOLS); HARDWARE; LOGIC CIRCUITS; SYSTEMS ANALYSIS; VLSI CIRCUITS;

CIRCUIT FAULTS; CIRCUIT TESTING; CONCURRENT ERROR DETECTION; DELAY; ELECTRICAL FAULT DETECTIONS; HARDWARE OVERHEADS; PARTIAL REPLICATION; PREDICTION FUNCTION;

FAULT DETECTION;

EID: 84941330228     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183132     Document Type: Conference Paper

References (13)

1. R. Sharma and K. K. Saluja, "An implementation and analysis of a concurrent built-in self-test technique," in Fault Tolerant Computing Symposium, 1988, pp. 164-169.
2. N. K. Jha and S.-J. Wang, "Design and synthesis of self-checking VLSI circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 6, pp. 878-887, 1993.
3. N. A. Touba and E. J. McCluskey, "Logic synthesis of multilevel circuits with concurrent error detection," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 7, pp. 783-789, 1997.
4. C. Zeng, N. Saxena, and E. J. McCluskey, "Finite state machine synthesis with concurrent error detection," in International Test Conference, 1999, pp. 672-679.
5. A. Chatterjee and R. K. Roy, "Concurrent error detection in non-linear digital circuits with applications to adaptive filters," in International Conference on Computer Design, 1993, pp. 606-609.
6. I. Bayraktaroglu and A. Orailoglu, "Low-cost on-line test for digital filters," in VLSI Test Symposium, 1999, pp. 446-451.
7. Y. Makris, I. Bayraktaroglu, and A. Orailoglu, "Invariance-based on-line test for RTL controller-datapath circuits," in VLSI Test Symposium, 2000, pp. 459-464.
8. C. E. Shannon, "The synthesis of two-terminal switching circuits," Bell System Technical Journal, vol. 28, pp. 59-98, 1949.
9. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldahna, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli, "SIS: a system for sequential circuit synthesis," ERL MEMO. No. UCB/ERL M92/41, EECS UC Berkeley CA 94720, 1992.
10. "ISCAS'89 benchmark circuits information," Available from http://www.cbl.ncsu.edu.
11. "ATALANTA combinational test generation tool," Available from http://www.ee.vt.edu/ha/cadtools.
12. H. K. Lee and D. S. Ha, "HOPE: An efficient parallel fault simulator for synchronous sequential circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 9, pp. 1048-1058, 1996.
13. T. Niermann and J. H. Patel, "HITEC: A test generation package for sequential circuits," in European Conference on Design Automation, 1992, pp. 214-218.