Implementation and analysis of a concurrent built-in self-test technique.

Digest of Papers - FTCS (Fault-Tolerant Computing Symposium)

Volumn , Issue , 1988, Pages 164-169

  Sharma, Rajiv ^a   Saluja, Kewal K ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUITS -- AUTOMATIC TESTING;

ARITHMETIC LOGIC UNIT; CMOS CIRCUITS; CONCURRENT BUILT-IN SELF-TEST; INTERMITTENT FAULTS; TRANSIENT FAULTS;

LOGIC CIRCUITS, COMBINATORIAL;

EID: 0024128168     PISSN: 07313071     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)