-
1
-
-
0031366763
-
Instruction buffering to reduce power in processors for signal processing
-
December
-
R. S. Bajwa, M. H. H. Kojima, D. Gorny, K. Nitta, A. Shridhar, K. Seki, and K. Sasaki. Instruction buffering to reduce power in processors for signal processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(4), December 1997.
-
(1997)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.5
, Issue.4
-
-
Bajwa, R.S.1
Kojima, M.H.H.2
Gorny, D.3
Nitta, K.4
Shridhar, A.5
Seki, K.6
Sasaki, K.7
-
2
-
-
0033723926
-
Architectural and compiler techniques for energy reduction in high-performance microprocessors
-
June
-
N. E. Bellas, I. N. Hajj, C. D. Polychronopoulos, and G. Stamoulis. Architectural and compiler techniques for energy reduction in high-performance microprocessors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8(3), June 2000.
-
(2000)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.8
, pp. 3
-
-
Bellas, N.E.1
Hajj, I.N.2
Polychronopoulos, C.D.3
Stamoulis, G.4
-
3
-
-
0033719421
-
Wattch: A framework for architectural-level power analysis and optimizations
-
Vancouver, British Columbia, June
-
D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th International Symposium on Computer Architecture (ISCA), Vancouver, British Columbia, June 2000.
-
(2000)
Proceedings of the 27th International Symposium on Computer Architecture (ISCA)
-
-
Brooks, D.1
Tiwari, V.2
Martonosi, M.3
-
4
-
-
0036294454
-
Drowsy caches: Simple techniques for reducing leakage power
-
K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge. Drowsy caches: Simple techniques for reducing leakage power. In Proceedings of the 27th International Symposium on Computer Architecture (ISCA), 2002.
-
(2002)
Proceedings of the 27th International Symposium on Computer Architecture (ISCA)
-
-
Flautner, K.1
Kim, N.S.2
Martin, S.3
Blaauw, D.4
Mudge, T.5
-
5
-
-
84962779213
-
Mibench: A free, commercially representative embedded benchmark suite
-
December
-
M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. Mibench: A free, commercially representative embedded benchmark suite. IEEE 4th Annual Workshop on Workload Characterization, December 2001.
-
(2001)
IEEE 4th Annual Workshop on Workload Characterization
-
-
Guthaus, M.R.1
Ringenberg, J.S.2
Ernst, D.3
Austin, T.M.4
Mudge, T.5
Brown, R.B.6
-
6
-
-
1542269318
-
Exploiting program hotspots and code sequentiality for instruction cache leakage management
-
Seoul, Korea, August
-
J. S. Hu, A. Nadgir, N. Vijaykrishnan, M. J. Irwin, and M. Kandemir. Exploiting program hotspots and code sequentiality for instruction cache leakage management. In Proc. of the International Symposium on Low Power Electronics and Design (ISLPED'03), Seoul, Korea, August 2003.
-
(2003)
Proc. of the International Symposium on Low Power Electronics and Design (ISLPED'03)
-
-
Hu, J.S.1
Nadgir, A.2
Vijaykrishnan, N.3
Irwin, M.J.4
Kandemir, M.5
-
8
-
-
0034856732
-
Cache decay: Exploiting generational behavior to reduce cache leakage power
-
Goteborg, Sweden, June
-
S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: Exploiting generational behavior to reduce cache leakage power. In Proceedings of the 28th International Symposium on Computer Architecture (ISCA), Goteborg, Sweden, June 2001.
-
(2001)
Proceedings of the 28th International Symposium on Computer Architecture (ISCA)
-
-
Kaxiras, S.1
Hu, Z.2
Martonosi, M.3
-
11
-
-
16244415729
-
Instruction fetch energy reduction using loop caches for embedded applications with small tight loops
-
August
-
L. H. Lee, W. Moyer, and J. Arends. Instruction fetch energy reduction using loop caches for embedded applications with small tight loops. In Proceedings of International Symposium on Low Power Design, pages 63-68, August 1999.
-
(1999)
Proceedings of International Symposium on Low Power Design
, pp. 63-68
-
-
Lee, L.H.1
Moyer, W.2
Arends, J.3
-
12
-
-
0032629113
-
A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization
-
May
-
M. C. Merten, A. R. Trick, C. N. George, J. C. Gyllenhaal, and W. W. Hwu. A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization. In Proceedings of International Symposium Computer Architecture, pages 136-147, May 1999.
-
(1999)
Proceedings of International Symposium Computer Architecture
, pp. 136-147
-
-
Merten, M.C.1
Trick, A.R.2
George, C.N.3
Gyllenhaal, J.C.4
Hwu, W.W.5
-
13
-
-
0030285348
-
A 160-mhz, 32-b, 0.5-w cmos risc microprocessor
-
November
-
J. Montanaro and et al. A 160-mhz, 32-b, 0.5-w cmos risc microprocessor. IEEE Journal of Solid State Circuits, 31(11):1703-1714, November 1996.
-
(1996)
IEEE Journal of Solid State Circuits
, vol.31
, Issue.11
, pp. 1703-1714
-
-
Montanaro, J.1
-
15
-
-
0035183294
-
Design of a predictive filter cache for energy savings in high performance processor architectures
-
Austin, Texas, USA
-
W. Tang, R. Gupta, and A. Nicolau. Design of a predictive filter cache for energy savings in high performance processor architectures. In International Conference on Computer Design(ICCD), Austin, Texas, USA, 2001.
-
(2001)
International Conference on Computer Design(ICCD)
-
-
Tang, W.1
Gupta, R.2
Nicolau, A.3
|