Using dynamic cache management techniques to reduce energy in general purpose processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 6, 2000, Pages 693-708

  Bellas, Nikolaos E ^a   Hajj, Ibrahim N ^b   Polychronopoulos, Constantine D ^b  

^a MOTOROLA INC   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; MICROCOMPUTERS; STORAGE ALLOCATION (COMPUTER);

DYNAMIC CACHE MANAGEMENT TECHNIQUE; INSTRUCTION CACHE; LOW POWER DESIGN; SYSTEM LEVEL;

CACHE MEMORY;

EID: 0034461271     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.902264     Document Type: Article

References (28)

1. D. Dobberpuhl, "The design of a high-performance low-power microprocessor," in Proc. Int. Symp. Low Power Electronics and Design, 1998, pp. 11-16.
2. S. Maane, D. Grunwald, and A. Klauser, "Pipeline gating: Speculation control for energy reduction," in Proc. Int. Symp. Computer Architecture, 1998, pp. 132-141.
3. J. Diguet, S. Wuytack, F. Catthoor, and H. De Man, "Formalized methodology for data reuse exploration in hierarchical memory mappings," in Proc. Int. Symp. Low Power Electronics and Design, Aug. 1997, pp. 30-35.
4. S. Wuytack, F. Catthoor, L. Nachtergaele, and H. De Man, "Power exploration for data dominated video applications," in Proc. Int. Symp. Low Power Electronics and Design, Aug. 1996, pp. 359-364.
5. S. Wuytack, F. Catthoor, and H. DeMan, "Transforming set data types to power optimal data structures," IEEE Trans. Computer-Aided Design, vol. 15, pp. 619-629, June 1996.
6. V. Tiwari, S. Malik, and A. Wolfe, "Power analysis of embedded software: A first step toward software power minimization," IEEE Trans. VLSI Syst., vol. 2, pp. 437-445, Dec. 1994.
7. V. Tiwari, S. Malik, A. Wolfe, and T. C. Lee, "Instruction level power analysis and optimization of software," J. VLSI Signal Processing, vol. 13, pp. 326-328, Aug. 1996.
8. R. Gonzales and M. Horowitz, "Energy dissipation in general purpose processors," IEEE J. Solid-State Circuits, vol. 31, pp. 1277-1284, Sept. 1996.
9. R. Bajwa, M. Hiraki, H. Kojima, D. Gorny, K. Nitta, A. Shridhar, K. Seki, and K. Sasaki, "Instruction buffering to reduce power in processors for signal processing," IEEE Trans. VLSI Syst., vol. 6, pp. 417-424, Dec. 1997.
10. R. Panwar and D. Rennels, "Reducing the frequency of tag compares for low power I-Cache design," in Proc. Int. Symp. Low Power Electronics and Design, Aug. 1995.
11. I. Bahar, G. Albera, and S. Manne, "Power and performance tradeoffs using various caching strategies," in Proc. Int. Symp. Low Power Electronics and Design, 1998, pp. 64-69.
12. J. Kin, M. Gupta, and W. Mangione-Smith, "The filter cache: An energy efficient memory structure," in Proc. Int. Symp. Micro architecture, Dec. 1997, pp. 184-193.
13. R. Fromm, S. Perissakis, N. Cardwell, C. Kozyrakis, B. McGaughy, D. Patterson, T. Anderson, and K. Yelick, "The energy efficiency of IRAM architectures," in Proc. Int. Symp. Computer Architecture, 1997, pp. 327-337.
14. J. Zawodny, E. Johnson, J. Brockman, and P. Kogge, "Cache-in-memory: A lower power alternative?," in Proc. Power-Driven Microarchitecture Workshop, ISCA, 1998, pp. 62-72.
15. N. Bellas, I. Hajj, C. Polychronopoulos, and G. Stamoulis, "Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors," in Proc. Int. Symp. Low Power Electronics and Design, Aug. 1998, pp. 70-75.
16. E. Jacobsen, E. Rotenberg, and J. Smith, "Assigning confidence to conditional branch prediction," in Proc. Int. Symp. Microarchitecture, 1996, pp. 142-152.
17. T. Johnson and W.-M. Hwu, "Run-time adaptive cache hierarchy management via reference analysis," in Proc. Int. Symp. Computer Architecture, 1997, pp. 315-326.
18. T. Johnson, M. Merten, and W.-M. Hwu, "Run-time spatial locality detection and estimation," in Proc. Int. Symp. Microarchitecture, 1997, pp. 57-64.
19. J. Hennesy and D. Patterson, Computer Architecture - A Quantitative Approach. San Mateo, CA: Morgan Kaufmann, 1996.
20. S. T. Pan, K. So, and J. T. Rahmeh, "Improving the accuracy of dynamic branch prediction using branch correlation," in Proc. Int. Conf. Architectural Support for Programming Languages and Operating Systems, 1992, pp. 76-84.
21. S. McFarling, "Combining branch predictors,", Tech. Rep., DEC WRL 93/5, June 1993.
22. T. Y. Yeh and Y. N. Patt, "A comparison of dynamic branch predictors that use two levels of branch history," in Proc. Int. Symp. Computer Architecture, 1993, pp. 257-266.
23. D. Grunwald, A. Klauser, S. Manne, and A. Plezskun, "Confidence estimation for speculation control," in Proc. Int. Symp. Computer Architecture, 1998, pp. 122-131.
24. J. E. Veenatra and R. J. Fowler, "MINT: A front end for efficient simulation of shared-memory multiprocessors," in Proc. 2nd Int. Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), 1994, pp. 201-207.
25. SpeedShop User's Guide: Silicon Graphics, Inc., 1996.
26. G. Kane and J. Heinrich, MIPS RISC Architecture. Englewood Cliffs, NJ: Prentice-Hall, 1992.
27. S. Wilson and N. Jouppi, "An enhanced access and cycle time model for on-chip caches,", Tech. Rep., DEC WRL 93/5, July 1994.
28. N. Bellas, I. Hajj, and C. Polychropoulos, "A detailed, transistor-level energy model for SRAM-based caches," in Proc. Int. Symp. Circuits and Systems, 1999, pp. 198-201.