Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs

IEEE International Reliability Physics Symposium Proceedings

Volumn 2004-January, Issue January, 2004, Pages 130-134

  Chatty, K ^a   Cottrell, P ^a   Gauthier, R ^a   Muhammad, M ^a   Stellari, F ^b   Weger, A ^b   Song, P ^b   McManus, M ^b  

^a IBM MICROELECTRONICS   (United States)

^b IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN;

CABLE DISCHARGE EVENTS; DC CURRENT; LATCH-UPS; MODEL-BASED OPC; PEAK CURRENTS; PHYSICAL DESIGN; TEST CHIPS; TRANSIENT PULSE;

INTEGRATED CIRCUIT DESIGN;

EID: 84932133311     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2004.1315313     Document Type: Conference Paper

References (12)

1. ITRS 2001 Edition, http://public.itrs.net
2. R. Troutman, "Latchup in CMOS Technology", Kluwer Academic Publishers, 1986.
3. M. J. Hargrove, S. Voldman, R. Gauthier, J. Brown, K. Duncan, W. Craig, "Latchup in CMOS Technology", IEEE International Reliability Physics Symposium Proceedings, 1998.
4. W. Morris, "Latchup in CMOS", 2003 IEEE International Reliability Physics Symposium Proceedings, 2003, pp.76-84.
5. "IC Latch-Up Test, E1A/JEDEC Standard", http://www.jedec.oig, 1997, pp. 1-18.
6. "Cable Discharge Event in Local Area Network", http-//www.intel.com/dssign/Qetwotk/products/LAN, 2001, pp. 1-12.
7. A. Weger, S. H. Voldman, F. Stellari, P. Song, P. Sanda and M, K. McManus, "Transmission Line Picosecond Imaging Circuit Analysis Methodology for Evaluation of Electrostatic Discharge and Latchup", 2003 IEEE International Reliability Physics Symposium Proceedings, 2003, pp.99-104.
8. F. Stellari, P. Song, M. K. McManus, A.J. Weger, R.J. Gauthier, K. Chatty, M. Muhammad and P. Sanda, Study of Critical Factots Determining Latchup Sensitivity of ICs using Emission Microscopy, Proc. of International Symposium for Testing and Failure Analysis (ISTFA), 2003, pp. 19-24.
9. F. Stellari, P. Song, M. K. McMacus, A. J. Weger, R. Gauthier, K. Chatty, T. Muhammad, P. Sanda, P. Wu and S. Wilson, "Latchup Anary si s U sing Tmission Microscopy", Proc. of European Symposium on Reliability of Tlectron Devices (ESREF), 2003, pp. 1603-1608.
10. F. Stellari, P. Song, M. K. McManus, R. Gauthier, A. J. Weger, K. Chatty, T. Muhammad and P. Sanda, "Optical and Electrical Testing of Latchup Tn I/O Interlace Circuits", Proc. of International Test Conference (ITC), 2003, pp. 236-245.
11. L. K. Han et al., "A Modular 0.13um Bulk CMOS Technology for High Tower and Lowe Power Applications", VLSI Proceedings, 2000, pp. 12-13.
12. R. Gauthier, W. Stadler, K. Esmark, P. Riess, A. Salman, M. Muhammad Tnd C. Putnam., "Evaluation of Diode Based and NMOS/inpn-Based TSD Protection Strategies in a Triple Gate Oxide Thickness 0.13um TMOS Logic Technology", EOS/ESD Symposium, 2001, pp. 205-215.