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Volumn , Issue , 2014, Pages 650-653

An energy efficient multi-bit TSV transmitter using capacitive coupling

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CHIP SCALE PACKAGES; CIRCUIT SIMULATION; ENERGY EFFICIENCY; INTEGRATED CIRCUIT INTERCONNECTS; SUBSTRATES; THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84925436749     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2014.7050069     Document Type: Conference Paper
Times cited : (4)

References (7)
  • 1
    • 84866840097 scopus 로고    scopus 로고
    • 6 Tbps/W, 1 Tbps/mm2, 3D interconnect using adaptive timing control and low capacitance TSV
    • feb. 2 2012
    • F. Furuta and K. Osada, "6 Tbps/W, 1 Tbps/mm2, 3D interconnect using adaptive timing control and low capacitance TSV," in 3D Systems Integration Conference (3DIC), 2011 IEEE International, 31 2012-feb. 2 2012, pp. 1-4.
    • (2012) 3D Systems Integration Conference (3DIC), 2011 IEEE International , vol.31 , pp. 1-4
    • Furuta, F.1    Osada, K.2
  • 7
    • 78650018928 scopus 로고    scopus 로고
    • Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs
    • dec
    • C. Xu, H. Li, R. Suaya, and K. Banerjee, "Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs," Electron Devices, IEEE Transactions on, vol. 57, no. 12, pp. 3405-3417, dec. 2010.
    • (2010) Electron Devices, IEEE Transactions on , vol.57 , Issue.12 , pp. 3405-3417
    • Xu, C.1    Li, H.2    Suaya, R.3    Banerjee, K.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.