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Volumn , Issue , 2011, Pages
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6 Tbps/W, 1 Tbps/mm 2, 3D interconnect using adaptive timing control and low capacitance TSV
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Author keywords
[No Author keywords available]
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Indexed keywords
3D INTERCONNECT;
CIRCUIT DESIGNS;
DATA-RATE;
INTERCONNECT PERFORMANCE;
LOW VOLTAGES;
PARASITIC CAPACITANCE;
POWER EFFICIENCY;
THROUGH-SILICON-VIA;
TIMING CONTROL;
TIMING SIGNALS;
INTEGRATED CIRCUIT MANUFACTURE;
THREE DIMENSIONAL COMPUTER GRAPHICS;
TIMING CIRCUITS;
CAPACITANCE;
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EID: 84866840097
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/3DIC.2012.6262963 Document Type: Conference Paper |
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Times cited : (5)
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References (2)
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