A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 180-181

  Walter, Dennis ^a   Höppner, Sebastian ^a   Eisenreich, Holger ^a   Ellguth, Georg ^a   Henker, Stephan ^a   Hänzsche, Stefan ^a   Schüffny, René ^a   Winter, Markus ^a   Fettweis, Gerhard ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH REQUIREMENT; CLOCK SIGNAL; DATA SYNCHRONIZATION; DYNAMIC VOLTAGE AND FREQUENCY SCALING; ENERGY-PER-BIT; FEATURE SIZES; HIGH BANDWIDTH; HIGH-SPEED; LOW SWING; LOW-PASS; ON CHIP COMMUNICATION; ON CHIPS; POWER REDUCTIONS; PRE-EMPHASIS; SYSTEM ARCHITECTURES;

BANDWIDTH; BUFFER STORAGE; ELECTRIC CLOCKS; ENERGY EFFICIENCY; WIRE;

MICROPROCESSOR CHIPS;

EID: 84860697517     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176902     Document Type: Conference Paper

References (6)

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2. H. Ito, et al., "A Low-Latency and High-Power-Efficient On-Chip LVDS Transmission Line Interconnect for an RC Interconnect Alternative," IEEE International Interconnect Technology Conf., pp. 193-195, 2007.
3. L. Zhang, et al., "A 32-Gb/s On-Chip Bus with Driver Pre-Emphasis Signaling," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 17, no. 9, pp.1267-1274, 2009.
4. R. Ho, et al., "High Speed and Low Energy Capacitively Driven On-Chip Wires," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 52-60, 2008
5. J. Seo, et al., "High-Bandwidth and Low-Energy On-Chip Signaling with Adaptive Pre-Emphasis in 90nm CMOS," ISSCC Dig. Tech. Papers, pp.182-183, 2010.
6. B. Kim, V. Stojanovic, "A 4Gb/s/ch 356fJ/b 10mm Equalized On-Chip Interconnect with Nonlinear Charge-Injecting Transmit Filter and Transimpedance Receiver in 90nm CMOS," ISSCC Dig. Tech Papers, pp. 66-67, 2009.