A 6-bit drift-resilient readout scheme for multi-level phase-change memory

2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

Volumn , Issue , 2015, Pages 137-140

  Athmanathan, Aravinthan ^a,c   Stanisavljevic, Milos ^a   Cheon, Junho ^b   Kang, Seokjoon ^b   Ahn, Changyong ^b   Yoon, Junghyuk ^b   Shin, Minchul ^b   Kim, Taekseung ^b   Papandreou, Nikolaos ^a   Pozidis, Haris ^a   Eleftheriou, Evangelos ^a  

^a IBM RESEARCH ZURICH   (Switzerland)

^b Hynix Semiconductor Inc   (South Korea)

^c EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; CYTOLOGY; READOUT SYSTEMS;

BIG DATA APPLICATIONS; EFFICIENT IMPLEMENTATION; ELECTRICAL RESISTANCES; IV CHARACTERISTICS; MEMORY TECHNOLOGY; MULTIPLE-LEVEL CELLS; NON-VOLATILE MEMORY APPLICATION; RESISTANCE DRIFTS;

PHASE CHANGE MEMORY;

EID: 84922567710     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2014.7008879     Document Type: Conference Paper

References (11)

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