Device, circuit and system-level analysis of noise in multi-bit phase-change memory

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2010, Pages

  Close, G F ^a   Frey, U ^a   Breitwisch, M ^b   Lung, H L ^c   Lam, C ^b   Hagleitner, C ^a   Eleftheriou, E ^a  

^a IBM RESEARCH ZURICH   (Switzerland)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c Macronix Nternational Co Ltd   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BITLINE CAPACITANCE; CELL CURRENT; CIRCUIT LEVELS; CRITICAL ELEMENTS; DATA INTEGRITY; ELECTRONIC READOUT; IMPACT OF NOISE; MULTI-BITS; MULTI-LEVEL; PHASE CHANGES; PROTOTYPE CHIP; SYSTEM-LEVEL ANALYSIS;

ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; ELECTRON DEVICES; PHASE CHANGE MEMORY; READOUT SYSTEMS; VOLTAGE REGULATORS;

BIT ERROR RATE;

EID: 79951822603     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2010.5703445     Document Type: Conference Paper

References (5)

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3. D. Fugazza, D. Ielmini, et al., Proc. IEDM, pp. 723-726, 2009.
4. M. Breitwisch, T. Nirschl, et al., Proc. Symp. VLSI Tech., pp. 100-101, 2007.
5. T. Nirschl, J. B. Philipp, et al., Proc. IEDM, pp. 461-464, 2007.