LastingNVCache: A technique for improving the lifetime of non-volatile caches

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn , Issue , 2014, Pages 534-540

  Mittal, Sparsh ^a   Vetter, Jeffrey S ^a,b   Li, Dong ^a  

^a OAK RIDGE NATIONAL LABORATORY   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

device lifetime; intra set write variation; microarchitectural technique; Non volatile memory (NVM); wear leveling; write endurance

Indexed keywords

NONVOLATILE STORAGE; RRAM; STATIC RANDOM ACCESS STORAGE;

DEVICE LIFETIME; INTRA-SET WRITE VARIATION; MICROARCHITECTURAL TECHNIQUE; NON-VOLATILE MEMORY; WEAR LEVELING; WRITE ENDURANCES;

CACHE MEMORY;

EID: 84908157659     PISSN: 21593469     EISSN: 21593477     Source Type: Book    
DOI: 10.1109/ISVLSI.2014.69     Document Type: Conference Paper

References (24)

1. Intel, http://ark.intel.com/products/53580/.
2. S. Li et al., "McPAT: an integrated power, area, and timing modeling framework for multicore and many-core architectures," in MICRO, 2009, pp. 469-480.
3. Y. Chen et al., "On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations," J. Emerg. Technol. Comput. Syst., vol. 9, no. 2, pp. 16:1-16:22, 2013.
4. S. Mittal, "Using cache-coloring to mitigate inter-set write variation in non-volatile caches," Iowa State University, Tech. Rep., 2013.
5. Y. Joo et al., "Energy-and endurance-aware design of phase change memory caches," in DATE, 2010, pp. 136-141.
6. X. Wu et al., "Hybrid cache architecture with disparate memory technologies," in ISCA, 2009, pp. 34-45.
7. G. Sun et al., "A novel architecture of the 3D stacked MRAM L2 cache for CMPs," in HPCA, 2009.
8. M. Qureshi et al., Phase change memory: From devices to systems. Morgan & Claypool Publishers, 2011, vol. 6, no. 4.
9. S.-S. Sheu et al., "A 4Mb embedded SLC Resistive-RAM macro with 7.2 ns read-write random-access time and 160ns MLC-access capability," in ISSCC, 2011.
10. X. Dong et al., "NVSim: A circuit-level performance, energy, and area model for emerging nonvolatile memory," IEEE TCAD, 2012.
11. 2WAP: Improving non-volatile cache lifetime by reducing inter-and intra-set write variations," in HPCA, 2013.
12. Y.-B. Kim et al., "Bi-layered RRAM with unlimited endurance and extremely uniform switching," in VL-SIT. IEEE, 2011, pp. 52-53.
13. Y. Huai, "Spin-transfer torque MRAM (STT-MRAM): Challenges and prospects," AAPPS Bulletin, vol. 18, no. 6, pp. 33-40, 2008.
14. W. Zhang and T. Li, "Characterizing and mitigating the impact of process variations on phase change based memory systems," in MICRO, 2009, pp. 2-13.
15. S. Mittal et al., "WriteSmoothing: Improving Lifetime of Non-volatile Caches Using Intra-set Wear-leveling," in ACM GLSVLSI, 2014.
16. Q. Li et al., "Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache," ACM SIGPLAN Notices, pp. 109-118, 2012.
17. J. Ahn and K. Choi, "Lower-bits cache for low power STT-RAM caches," in ISCAS, 2012, pp. 480-483.
18. P. Zhou et al., "Energy reduction for STT-RAM using early write termination," in ICCAD, 2009, pp. 264-268.
19. T. E. Carlson et al., "Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulations," in SC, 2011.
20. S. Mittal et al., "FlexiWay: A Cache Energy Saving Technique Using Fine-grained Cache Reconfiguration," in ICCD, 2013.
21. S. Kaxiras et al., "Cache decay: exploiting generational behavior to reduce cache leakage power," in ISCA, 2001.
22. S. Mittal et al., "MASTER: A Multicore Cache Energy Saving Technique using Dynamic Cache Reconfiguration," IEEE TVLSI, 2013.
23. R. Manikantan et al., "Probabilistic shared cache management (PriSM)," in ISCA, 2012, pp. 428-439.
24. H.-H. S. Lee et al., "Eager writeback-a technique for improving bandwidth utilization," in MICRO, 2000.