Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache

ACM SIGPLAN Notices

Volumn 47, Issue 5, 2012, Pages 109-118

  Li, Qingan ^a   Zhao, Mengying ^b   Xue, Chun Jason ^b   He, Yanxiang ^c  

^a UNIVERSITY OF HONG KONG   (Hong Kong)

^b CITY UNIVERSITY OF HONG KONG   (Hong Kong)

^c WUHAN UNIVERSITY   (China)

Author keywords

Compiler; Data assignment; Hybrid cache

Indexed keywords

ASSIGNMENT TECHNIQUE; CACHE HIERARCHIES; COMPILER; COMPILER-ASSISTED; DATA ASSIGNMENT; DYNAMIC ENERGY; HIGH STORAGE DENSITY; HYBRID CACHE; LOW LEAKAGE POWER; MANAGEMENT STRATEGIES; MEMORY BLOCKS; ON-CHIP CACHE; SPIN TORQUE; WRITE OPERATIONS;

EMBEDDED SYSTEMS; ENERGY EFFICIENCY; ENERGY UTILIZATION; STATIC RANDOM ACCESS STORAGE;

COST REDUCTION;

EID: 84866340444     PISSN: 15232867     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

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