Lower-bits cache for low power STT-RAM caches

ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2012, Pages 480-483

  Ahn, Junwhan ^a   Choi, Kiyoung ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC POWER CONSUMPTION; L2 CACHE; LOW POWER; LOW STATIC POWER; LOW-POWER CONSUMPTION; NOVEL TECHNIQUES; POWER EFFICIENT; POWER SAVINGS; SPIN TRANSFER TORQUE;

CACHE MEMORY;

EID: 84866596192     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2012.6272069     Document Type: Conference Paper

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